Datasheet
© 2009 Microchip Technology Inc. DS41291F-page 97
PIC16F882/883/884/886/887
TABLE 8-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE
REFERENCE MODULES
REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN VROE VRR VRSS VR3 VR2 VR1 VR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VREN: Comparator C1 Voltage Reference Enable bit
1 =CV
REF circuit powered on
0 =CV
REF circuit powered down
bit 6 VROE: Comparator C2 Voltage Reference Enable bit
1 =CV
REF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2IN+ pin
0 =CV
REF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2IN+ pin
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 VRSS: Comparator V
REF Range Selection bit
1 = Comparator Reference Source, CV
RSRC = (VREF+) - (VREF-)
0 = Comparator Reference Source, CV
RSRC = VDD - VSS
bit 3-0 VR<3:0>: CVREF Value Selection 0 ≤ VR<3:0> ≤ 15
When V
RR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSEL
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
ANSELH
— — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 --11 1111
CM1CON0 C1ON C1OUT C1OE C1POL
— C1R C1CH1 C1CH0 0000 -000 0000 -000
CM2CON0 C2ON C2OUT C2OE C2POL
— C2R C2CH1 C2CH0 0000 -000 0000 -000
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL
— — T1GSS C2SYNC 0000 --10 0000 --10
INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE2
OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 0000 00-0 0000 00-0
PIR2
OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 0000 00-0 0000 00-0
PORTA
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu
PORTB
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
SRCON SR1 SR0 C1SEN C2SEN PULSS PULSR
— FVREN 0000 00-0 0000 00-0
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.