Datasheet

PIC16F882/883/884/886/887
DS41291F-page 320 © 2009 Microchip Technology Inc.
SSPCON (MSSP Control 1)......................................181
SSPCON2 (SSP Control 2).......................................182
SSPMSK (SSP Mask)...............................................208
SSPSTAT (SSP Status)............................................180
STATUS......................................................................29
T1CON........................................................................79
T2CON........................................................................82
TRISA (Tri-State PORTA)...........................................39
TRISB (Tri-State PORTB)...........................................48
TRISC (Tri-State PORTC) ..........................................53
TRISD (Tri-State PORTD) ..........................................57
TRISE (Tri-State PORTE)...........................................59
TXSTA (Transmit Status and Control) ......................160
VRCON (Voltage Reference Control) .........................97
WDTCON (Watchdog Timer Control)........................225
WPUB (Weak Pull-up PORTB) ...................................49
Reset.................................................................................212
Revision History ................................................................313
S
SCK...................................................................................183
SDI ....................................................................................183
SDO ..................................................................................183
Serial Clock, SCK..............................................................183
Serial Data In, SDI ............................................................183
Serial Data Out, SDO........................................................183
Serial Peripheral Interface. See SPI
Shoot-through Current ......................................................144
Slave Mode General Call Address Sequence...................192
Slave Select Synchronization............................................186
Slave Select, SS
...............................................................183
Sleep.................................................................................226
Wake-up....................................................................226
Wake-up Using Interrupts .........................................226
Software Simulator (MPLAB SIM).....................................242
SPBRG..............................................................................163
SPBRGH...........................................................................163
Special Event Trigger........................................................102
Special Function Registers .................................................22
SPI
Master Mode.............................................................185
Serial Clock...............................................................183
Serial Data In ............................................................183
Serial Data Out .........................................................183
Slave Select..............................................................183
SPI clock...................................................................185
SPI Mode ..................................................................183
SPI Bus Modes .................................................................188
SPI Mode
Associated Registers with SPI Operation .................188
Bus Mode Compatibility ............................................188
Effects of a Reset......................................................188
Enabling SPI I/O .......................................................184
Operation ..................................................................183
Sleep Operation ........................................................188
SPI Module
Slave Mode...............................................................186
Slave Select Synchronization ...................................186
Slave Synchronization Timing...................................186
Slave Timing with CKE = 0 .......................................187
Slave Timing with CKE = 1 .......................................187
SRCON Register.................................................................93
SS
.....................................................................................183
SSP
SSPBUF....................................................................185
SSPSR......................................................................185
SSPCON Register ............................................................ 181
SSPCON2 Register .......................................................... 182
SSPMSK Register ............................................................ 208
SSPOV ............................................................................. 198
SSPOV Status Flag .......................................................... 198
SSPSTAT Register........................................................... 180
R/W
Bit ..................................................................... 190
STATUS Register ............................................................... 29
T
T1CON Register ................................................................. 79
T2CON Register ................................................................. 82
Thermal Considerations.................................................... 253
Time-out Sequence .......................................................... 215
Timer0................................................................................. 73
Associated Registers.................................................. 75
External Clock............................................................. 74
Interrupt ...................................................................... 75
Operation.............................................................. 73, 76
Specifications ........................................................... 260
T0CKI ......................................................................... 74
Timer1................................................................................. 76
Associated Registers.................................................. 80
Asynchronous Counter Mode ..................................... 77
Reading and Writing........................................... 77
Interrupt ...................................................................... 78
Modes of Operation .................................................... 76
Operation During Sleep.............................................. 78
Oscillator..................................................................... 77
Prescaler .................................................................... 77
Specifications ........................................................... 260
Timer1 Gate
Inverting Gate ..................................................... 77
Selecting Source .......................................... 77, 91
SR Latch............................................................. 92
Synchronizing COUT w/Timer1 .......................... 91
TMR1H Register......................................................... 76
TMR1L Register.......................................................... 76
Timer2
Associated Registers.................................................. 82
Timers
Timer1
T1CON ............................................................... 79
Timer2
T2CON ............................................................... 82
Timing Diagrams
A/D Conversion......................................................... 265
A/D Conversion (Sleep Mode).................................. 265
Acknowledge Sequence Timing ............................... 201
Asynchronous Reception.......................................... 158
Asynchronous Transmission..................................... 154
Asynchronous Transmission (Back to Back) ............ 154
Auto Wake-up Bit (WUE) During Normal Operation. 168
Auto Wake-up Bit (WUE) During Sleep .................... 169
Automatic Baud Rate Calibration.............................. 167
Baud Rate Generator with Clock Arbitration............. 195
BRG Reset Due to SDA Arbitration .......................... 205
Brown-out Reset (BOR)............................................ 258
Brown-out Reset Situations ...................................... 214
Bus Collision
Start Condition Timing...................................... 204
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 206
Bus Collision During a Repeated Start
Condition (Case2)............................................. 206
Bus Collision During a Start Condition (SCL = 0) ..... 205