PIC16F882/883/884/886/887 Data Sheet 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F882/883/884/886/887 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology High-Performance RISC CPU: Peripheral Features: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes • 24/35 I/O Pins with Individual Direction Control: - High current source/sink for di
PIC16F882/883/884/886/887 Device Program Memory Data Memory I/O 10-bit A/D (ch) ECCP/ CCP EUSART MSSP Comparators Timers 8/16-bit 128 24 11 1/1 1 1 2 2/1 256 24 11 1/1 1 1 2 2/1 256 256 35 14 1/1 1 1 2 2/1 8192 368 256 24 11 1/1 1 1 2 2/1 8192 368 256 35 14 1/1 1 1 2 2/1 Flash (words) SRAM (bytes) EEPROM (bytes) PIC16F882 2048 128 PIC16F883 4096 256 PIC16F884 4096 PIC16F886 PIC16F887 DS41291F-page 2 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 Pin Diagrams – PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RE3/MCLR/VPP RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL TABLE 1: PIC16F882/883/886 28-pin PDIP, SOIC, SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/T1G RB4/AN11/P1D RB3/AN9/PGM/C12IN2RB2/AN8/P1B
PIC16F882/883/884/886/887 Pin Diagrams – PIC16F882/883/886, 28-Pin QFN 28 27 26 25 24 23 22 RA1/AN1/C12IN1RA0/AN0/ULPWU/C12IN0RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/T1G RB4/AN11/P1D 28-pin QFN 8 9 10 11 12 13 14 1 21 2 20 3 19 4 PIC16F882/883/886 18 5 17 6 16 15 7 RB3/AN9/PGM/C12IN2RB2/AN8/P1B RB1/AN10/P1C/C12IN3RB0/AN12/INT VDD VSS RC7/RX/DT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/
PIC16F882/883/884/886/887 TABLE 2: PIC16F882/883/886 28-PIN SUMMARY (QFN) I/O Pin Analog Comparators Timers ECCP EUSART MSSP Interrupt Pull-up Basic RA0 27 AN0/ULPWU C12IN0- — — — — — — — RA1 28 AN1 C12IN1- — — — — — — — RA2 1 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 2 AN3 C1IN+ — — — — — — VREF+ — RA4 3 — C1OUT T0CKI — — — — — RA5 4 AN4 C2OUT — — — SS — — — RA6 7 — — — — — — — — OSC2/CLKOUT RA7 6 — — — — — — — —
PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 40-Pin PDIP RE3/MCLR/VPP RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/AN5 RE1/AN6 RE2/AN7 VDD VSS RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RD0 RD1 DS41291F-page 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC16F884/887 40-pin PDIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/ICSPDAT RB6/ICSPCLK RB5/AN1
PIC16F882/883/884/886/887 TABLE 3: PIC16F884/887 40-PIN SUMMARY (PDIP) I/O Pin Analog Comparators Timers ECCP EUSART MSSP RA0 2 AN0/ULPWU C12IN0- — — — — Interrupt Pull-up — — Basic RA1 3 AN1 C12IN1- — — — — — — — RA2 4 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 5 AN3 C1IN+ — — — — — — VREF+ RA4 6 — C1OUT T0CKI — — — — — — RA5 7 AN4 C2OUT — — — SS — — — RA6 14 — — — — — — — — OSC2/CLKOUT — RA7 13 — — — — — — — — OSC
PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin QFN PIC16F884/887 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RA6/OSC2/CLKOUT RA7/OSC1/CLKIN VSS VSS NC VDD RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT RB3/AN9/PGM/C12IN2NC RB4/AN11 RB5/AN13/T1G RB6/ICSPCLK RB7/ICSPDAT RE3/MCLR/VPP RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3//VREF+/C1IN+ RC7/RX/DT RD4 RD5/P1B RD6/P1C RD7/P1D VSS VDD VDD RB0/AN12/INT RB1/AN1
PIC16F882/883/884/886/887 TABLE 4: PIC16F884/887 44-PIN SUMMARY (QFN) I/O Pin Analog Comparators Timers ECCP EUSART MSSP RA0 19 AN0/ULPWU C12IN0- — — — — Interrupt Pull-up — — Basic RA1 20 AN1 C12IN1- — — — — — — — RA2 21 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 22 AN3 C1IN+ — — — — — — VREF+ RA4 23 — C1OUT T0CKI — — — — — — RA5 24 AN4 C2OUT — — — SS — — — RA6 33 — — — — — — — — OSC2/CLKOUT RA7 32 — — — — — — — — O
PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin TQFP PIC16F884/887 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T1CKI RA6/OSC2/CLKOUT RA7/OSC1/CLKIN VSS VDD RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT NC NC RB4/AN11 RB5/AN13/T1G RB6/ICSPCLK RB7/ICSPDAT RE3/MCLR/VPP RA0/AN0/ULPWU/C12IN0RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3//VREF+/C1IN+ RC7/RX/DT RD4 RD5/P1B RD6/P1C RD7/P1D VSS VDD RB0/AN12/INT RB1/AN10/C12I
PIC16F882/883/884/886/887 TABLE 5: PIC16F884/887 44-PIN SUMMARY (TQFP) I/O Pin Analog Comparators Timers ECCP EUSART MSSP RA0 19 AN0/ULPWU C12IN0- — — — — Interrupt Pull-up — — Basic RA1 20 AN1 C12IN1- — — — — — — — RA2 21 AN2 C2IN+ — — — — — — VREF-/CVREF RA3 22 AN3 C1IN+ — — — — — — VREF+ RA4 23 — C1OUT T0CKI — — — — — — RA5 24 AN4 C2OUT — — — SS — — — RA6 31 — — — — — — — — OSC2/CLKOUT RA7 30 — — — — — — — —
PIC16F882/883/884/886/887 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Memory Organization ................................................................................................................................................................. 21 3.0 I/O Ports .........................................................................
PIC16F882/883/884/886/887 1.0 DEVICE OVERVIEW The PIC16F882/883/884/886/887 is covered by this data sheet. The PIC16F882/883/886 is available in 28pin PDIP, SOIC, SSOP and QFN packages. The PIC16F884/887 is available in a 40-pin PDIP and 44pin QFN and TQFP packages. Figure 1-1 shows the block diagram of PIC16F882/883/886 and Figure 1-2 shows a block diagram of the PIC16F884/887 device. Table 1-1 and Table 1-2 show the corresponding pinout descriptions. © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 FIGURE 1-1: PIC16F882/883/886 BLOCK DIAGRAM Configuration PORTA 13 8 Data Bus RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 Program Counter Flash 2K(2)/4K(1)/ 8K X 14 Program Memory Program Bus RAM 128(2)/256(1)/ 368 Bytes File Registers 8-Level Stack (13-Bit) 14 RAM Addr PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 9 Addr MUX Instruction Reg 7 Direct Addr Indirect Addr 8 FSR Reg PORTC STATUS Reg RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 8 3 MUX Power-up Timer Instruction Decode and Contro
PIC16F882/883/884/886/887 PIC16F884/PIC16F887 BLOCK DIAGRAM Configuration PORTA 13 8 Data Bus RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 Program Counter Flash 4K(1)/8K X 14 Program Memory Program Bus RAM 256(1)/368 Bytes File Registers 8-Level Stack (13-Bit) PORTB 14 RAM Addr RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 9 Addr MUX Instruction Reg 7 Direct Addr Indirect Addr 8 FSR Reg STATUS Reg PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 8 3 MUX Power-up Timer Instruction Decode and Control Oscillator Start-up Tim
PIC16F882/883/884/886/887 TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION Name RA0/AN0/ULPWU/C12IN0- RA1/AN1/C12IN1- RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RB0/AN12/INT RB1/AN10/P1C/C12IN3- RB2/AN8/P1B Legend: Function Input Type RA0 TTL Description CMOS General purpose I/O. AN0 AN — A/D Channel 0 input. ULPWU AN — Ultra Low-Power Wake-up input. — Comparator C1 or C2 negative input.
PIC16F882/883/884/886/887 TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION (CONTINUED) Name RB3/AN9/PGM/C12IN2- RB4/AN11/P1D RB5/AN13/T1G RB6/ICSPCLK RB7/ICSPDAT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RE3/MCLR/VPP Function Input Type RB3 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN9 AN — PGM ST — A/D Channel 9.
PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION Name RA0/AN0/ULPWU/C12IN0- RA1/AN1/C12IN1- RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RB0/AN12/INT RB1/AN10/C12IN3- Function Input Type RA0 TTL AN0 AN CMOS General purpose I/O. — A/D Channel 0 input. ULPWU AN — Ultra Low-Power Wake-up input. AN — Comparator C1 or C2 negative input.
PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED) Name RB4/AN11 RB5/AN13/T1G RB6/ICSPCLK RB7/ICSPDAT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK Function Input Type RB4 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN11 AN RB5 TTL — A/D Channel 11. AN13 AN — A/D Channel 13. T1G ST — Timer1 Gate input.
PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED) Function Input Type RD7/P1D RD7 TTL P1D AN RE0/AN5 RE0 TTL AN5 AN RE1/AN6 RE1 TTL AN6 AN RE2/AN7 RE2 TTL Name RE3/MCLR/VPP Output Type Description CMOS General purpose I/O. — PWM output. CMOS General purpose I/O. — A/D Channel 5. CMOS General purpose I/O. — A/D Channel 6. CMOS General purpose I/O. AN7 AN — A/D Channel 7. RE3 TTL — General purpose input.
PIC16F882/883/884/886/887 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F882/883/884/886/887 has a 13-bit program counter capable of addressing a 2K x 14 (0000h-07FFh) for the PIC16F882, 4K x 14 (0000h-0FFFh) for the PIC16F883/PIC16F884, and 8K x 14 (0000h-1FFFh) for the PIC16F886/PIC16F887 program memory space. Accessing a location above these boundaries will cause a wrap-around within the first 8K x 14 space.
PIC16F882/883/884/886/887 2.2 Data Memory Organization The data memory (see Figures 2-2 and 2-3) is partitioned into four banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. The General Purpose Registers, implemented as static RAM, are located in the last 96 locations of each Bank.
PIC16F882/883/884/886/887 FIGURE 2-4: PIC16F882 SPECIAL FUNCTION REGISTERS File File Address File Address File Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr.
PIC16F882/883/884/886/887 FIGURE 2-5: PIC16F883/PIC16F884 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr.
PIC16F882/883/884/886/887 FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS File File File File Address Address Address Address Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr.
PIC16F882/883/884/886/887 TABLE 2-1: Addr Name PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217 01h TMR0 Timer0 Module Register xxxx xxxx 73,217 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 37,217 03h STATUS 29,217 04h FSR 05h PORTA(3) 06h
PIC16F882/883/884/886/887 TABLE 2-2: Addr Name PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS 84h FSR RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 PD Z DC C Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO Indirect Data Memory Addr
PIC16F882/883/884/886/887 TABLE 2-3: Addr PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 37,217 101h TMR0 Timer0 Module Register xxxx xxxx 73,217 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 37,217 103h STATUS 0001 1xxx 29,217 IRP RP1 RP0
PIC16F882/883/884/886/887 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (GPR and SFR) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F882/883/884/886/887 2.2.2.2 OPTION Register Note: The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: • • • • To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 6.3 “Timer1 Prescaler”.
PIC16F882/883/884/886/887 2.2.2.3 INTCON Register Note: The INTCON register, shown in Register 2-3, is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register.
PIC16F882/883/884/886/887 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16F882/883/884/886/887 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as shown in Register 2-5. REGISTER 2-5: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16F882/883/884/886/887 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-6. REGISTER 2-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F882/883/884/886/887 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as shown in Register 2-7. REGISTER 2-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F882/883/884/886/887 2.2.2.8 PCON Register The Power Control (PCON) register (see Register 2-8) contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR.
PIC16F882/883/884/886/887 2.3 2.3.2 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-7 shows the two situations for the loading of the PC. The upper example in Figure 2-7 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F882/883/884/886/887 FIGURE 2-8: DIRECT/INDIRECT ADDRESSING PIC16F882/883/884/886/887 Direct Addressing RP1 RP0 6 Bank Select From Opcode Indirect Addressing 0 IRP 7 Bank Select Location Select 00 01 10 File Select Register 0 Location Select 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Note: DS41291F-page 38 Bank 1 Bank 2 Bank 3 For memory map detail, see Figures 2-2 and 2-3. © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 3.0 I/O PORTS operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. There are as many as thirty-five general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 3.
PIC16F882/883/884/886/887 3.2 Additional Pin Functions RA0 also has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 3.2.1 ANSEL REGISTER The ANSEL register (Register 3-3) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions.
PIC16F882/883/884/886/887 3.2.2 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink, which can be used to discharge a capacitor on RA0. Follow these steps to use this feature: a) b) c) d) e) Charge the capacitor on RA0 by configuring the RA0 pin to output (= 1).
PIC16F882/883/884/886/887 3.2.3 PIN DESCRIPTIONS AND DIAGRAMS 3.2.3.1 Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D Converter (ADC), refer to the appropriate section in this data sheet. FIGURE 3-1: RA0/AN0/ULPWU/C12IN0- Figure 3-1 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.2.3.2 3.2.3.3 RA1/AN1/C12IN1- RA2/AN2/VREF-/CVREF/C2IN+ Figure 3-2 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 3-3 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.2.3.4 RA3/AN3/VREF+/C1IN+ 3.2.3.5 RA4/T0CKI/C1OUT Figure 3-4 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 3-5 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.2.3.6 3.2.3.7 RA5/AN4/SS/C2OUT RA6/OSC2/CLKOUT Figure 3-6 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 3-7 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.2.3.8 RA7/OSC1/CLKIN Figure 3-8 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.3 PORTB and TRISB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 3-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16F882/883/884/886/887 REGISTER 3-4: ANSELH: ANALOG SELECT HIGH REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANS<13:8>: Analog Select bits Analog select between analog or digital function on pins AN<13:8>, respectively.
PIC16F882/883/884/886/887 REGISTER 3-7: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown WPUB<7:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global RBPU bit of the OPTION register must be cleared
PIC16F882/883/884/886/887 3.4.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the SSP, I2C or interrupts, refer to the appropriate section in this data sheet. 3.4.4.1 FIGURE 3-9: Data Bus D WR WPUB BLOCK DIAGRAM OF RB<3:0> Q CK RBPU CCP1OUT Enable D WR PORTB Note 1: P1C is available on PIC16F882/883/886 only.
PIC16F882/883/884/886/887 3.4.4.5 RB4/AN11/P1D(1) 3.4.4.7 RB6/ICSPCLK Figure 3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a PWM output(1) • a general purpose I/O • In-Circuit Serial Programming clock 3.4.4.8 Note 1: P1D is available on PIC16F882/883/886 only. 3.4.4.
PIC16F882/883/884/886/887 TABLE 3-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 5 Bit 4 — — ANS13 ANS12 P1M1 P1M0 DC1B1 DC1B0 ANSELH CCP1CON Bit 6 MC1OUT MC2OUT C1RSEL C2RSEL CM2CON1 IOCB Bit 2 Bit 1 Bit 0 Value on POR, BOR ANS11 ANS10 ANS9 ANS8 --11 1111 --11 1111 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 — — T1GSS IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIC16F882/883/884/886/887 3.5 PORTC and TRISC Registers The TRISC register (Register 3-10) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 3-10).
PIC16F882/883/884/886/887 3.5.1 3.5.3 RC0/T1OSO/T1CKI RC2/P1A/CCP1 Figure 3-11 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 3-13 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.5.4 RC3/SCK/SCL 3.5.6 RC5/SDO Figure 3-14 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 3-16 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.5.7 3.5.8 RC6/TX/CK RC7/RX/DT Figure 3-17 shows the diagram for this pin. This pin is configurable to function as one of the following: Figure 3-18 shows the diagram for this pin.
PIC16F882/883/884/886/887 3.6 PORTD and TRISD Registers The TRISD register (Register 3-12) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTD(1) is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 3-12).
PIC16F882/883/884/886/887 3.6.1 RD<4:0> 3.6.3 Figure 3-19 shows the diagram for these pins. These pins are configured to function as general purpose I/O’s. Note: Figure 3-20 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a PWM output RD<4:0> is available on PIC16F884/887 only. FIGURE 3-19: RD6/P1C(1) Note 1: RD6/P1C is available on PIC16F884/887 only. See RB1/AN10/P1C/C12IN3- for this function on PIC16F882/883/886.
PIC16F882/883/884/886/887 3.7 PORTE and TRISE Registers The TRISE register (Register 3-14) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTE(1) is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE.
PIC16F882/883/884/886/887 RE0/AN5(1) 3.7.1 3.7.4 RE3/MCLR/VPP This pin is configurable to function as one of the following: Figure 3-22 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a general purpose input • as Master Clear Reset with weak pull-up Note 1: RE0/AN5 is available on PIC16F884/887 only. FIGURE 3-22: BLOCK DIAGRAM OF RE3 VDD RE1/AN6(1) 3.7.
PIC16F882/883/884/886/887 4.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) The oscillator module can be configured in one of eight clock modes. 4.1 Overview 1. 2. 3. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module. 4. 5.
PIC16F882/883/884/886/887 4.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 4-1) controls the system clock and frequency selection options.
PIC16F882/883/884/886/887 4.3 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the oscillator module.
PIC16F882/883/884/886/887 4.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.
PIC16F882/883/884/886/887 4.4.4 EXTERNAL RC MODES 4.5 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4.
PIC16F882/883/884/886/887 4.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 4-2: When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
PIC16F882/883/884/886/887 4.5.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 4.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
PIC16F882/883/884/886/887 FIGURE 4-6: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <2:0> ≠0 =0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC ≠0 IRCF <2:0> =0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <2:0> =0 ¼0 System Clock DS41291F-page 68 ©
PIC16F882/883/884/886/887 4.6 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. 4.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals.
PIC16F882/883/884/886/887 4.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or the internal oscillator. FIGURE 4-7: TWO-SPEED START-UP HFINTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS41291F-page 70 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 4.8 4.8.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word Register 1 (CONFIG1). The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and RCIO).
PIC16F882/883/884/886/887 FIGURE 4-9: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 CONFIG1(2) OSCTUNE Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
PIC16F882/883/884/886/887 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 5.1.
PIC16F882/883/884/886/887 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256.
PIC16F882/883/884/886/887 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrup
PIC16F882/883/884/886/887 6.
PIC16F882/883/884/886/887 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI.
PIC16F882/883/884/886/887 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • PEIE bit of the INTCON register • GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 6.
PIC16F882/883/884/886/887 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16F882/883/884/886/887 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL GIE PEIE T0IE INTE PIE1 — ADIE RCIE TXIE PIR1 — ADIF RCIF TXIF INTCON Bit 3 Value on POR, BOR Value on all other Resets Bit 2 Bit 1 Bit 0 — — T1GSS C2SYNC 0000 --10 0000 --10 RBIE T0IF INTF RBIF 0000 000x 0000 000x SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 u
PIC16F882/883/884/886/887 7.0 TIMER2 MODULE The Timer2 module is an eight-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’.
PIC16F882/883/884/886/887 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 =
PIC16F882/883/884/886/887 8.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution.
PIC16F882/883/884/886/887 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> C1POL 2 D Q1 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 Q EN To Data Bus RD_CM1CON0 Set C1IF D Q3*RD_CM1CON0 Q EN CL To PWM Logic Reset C1ON(1) C1R C1IN+ FixedRef CVREF 0 MUX 1 C1VIN- C1 C1VIN+ + 0 MUX C1VREF 1 C1OUT C1OUT (to SR Latch) C1POL C1RSEL Note 1: 2: 3: FIGURE 8-3: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
PIC16F882/883/884/886/887 8.2 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs.
PIC16F882/883/884/886/887 8.4 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figures 8-2 and 8-3). One latch is updated with the comparator output level when the CMxCON0 register is read. This latch retains the value until the next read of the CMxCON0 register or the occurrence of a Reset.
PIC16F882/883/884/886/887 8.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 17.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register.
PIC16F882/883/884/886/887 REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OU
PIC16F882/883/884/886/887 REGISTER 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OU
PIC16F882/883/884/886/887 8.7 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-6. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC16F882/883/884/886/887 8.8 Additional Comparator Features 8.8.2 There are three additional comparator features: • Timer1 count enable (gate) • Synchronizing output with Timer1 • Simultaneous read of comparator outputs 8.8.1 COMPARATOR C2 GATING TIMER1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CM2CON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled.
PIC16F882/883/884/886/887 8.9 8.9.2 Comparator SR Latch The SR<1:0> bits of the SRCON register control the latch output multiplexers and determine four possible output configurations. In these four configurations, the CxOUT I/O port logic is connected to: The SR latch module provides additional control of the comparator outputs. The module consists of a single SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs.
PIC16F882/883/884/886/887 REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER R/W-0 R/W-0 (2) (2) SR1 SR0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 R/W-0 C1SEN C2REN PULSS PULSR — FVREN bit 7 bit 0 Legend: S = Bit is set only - R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SR1: SR Latch Configuration bit(2) 1 = C2OUT pin is the latch Q output 0 = C2OUT pin is the C2 comparator output bit 6
PIC16F882/883/884/886/887 8.10 Comparator Voltage Reference 8.10.3 OUTPUT CLAMPED TO VSS The comparator voltage reference module provides an internally generated voltage reference for the comparators. The following features are available: The CVREF output voltage can be set to Vss with no power consumption by clearing the FVREN bit of the VRCON register. • • • • • This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current.
PIC16F882/883/884/886/887 FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages VREF+ VRSS = 1 8R R R R R VRSS = 0 VRR 8R VDD Analog MUX VREFVRSS = 1 15 CVREF VRSS = 0 To Comparators and ADC Module 0 VR<3:0> VROE 4 VREN C1RSEL C2RSEL CVREF FVREN Sleep HFINTOSC enable FixedRef EN Fixed Voltage Reference 0.
PIC16F882/883/884/886/887 TABLE 8-2: COMPARATOR AND ADC VOLTAGE REFERENCE PRIORITY RA3 RA2 Comp. Reference (+) Comp.
PIC16F882/883/884/886/887 REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR VRSS VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: Comparator C1 Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 VROE: Comparator C2 Voltage Refe
PIC16F882/883/884/886/887 NOTES: DS41291F-page 98 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16F882/883/884/886/887 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits.
PIC16F882/883/884/886/887 TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<1:0> FOSC/2 20 MHz 00 FOSC/8 01 8 MHz 100 ns (2) 250 ns 400 ns (2) 1.0 μs 500 ns 10 1.6 μs 4.0 μs FRC 11 2-6 μs(1,4) 2-6 μs(1,4) (2) 2.0 μs (2) FOSC/32 Legend: Note 1: 2: 3: 4: 4 MHz (2) 8.0 μs (3) 2-6 μs(1,4) 1 MHz 2.0 μs 8.0 μs(3) 32.0 μs(3) 2-6 μs(1,4) Shaded cells are outside of recommended range.
PIC16F882/883/884/886/887 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-3 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 LSB bit 0 Unimplemented: Read as ‘0’ 9.2 9.2.
PIC16F882/883/884/886/887 9.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16F882/883/884/886/887 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. Note: For ANSEL and ANSELH registers, see Register 3-3 and Register 3-4, respectively.
PIC16F882/883/884/886/887 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 ADFM — VCFG1 VCFG0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference bit 1 = VREF- pin 0 = VSS bit 4 VCFG0: Volt
PIC16F882/883/884/886/887 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-4: ADRESL: ADC RESULT REGI
PIC16F882/883/884/886/887 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4.
PIC16F882/883/884/886/887 FIGURE 9-4: ANALOG INPUT MODEL VDD ANx Rs CPIN 5 pF VA VT = 0.6V VT = 0.6V RIC ≤ 1k Sampling Switch SS Rss I LEAKAGE(1) ± 500 nA CHOLD = 10 pF VSS/VREF- Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: 6V 5V VDD 4V 3V 2V RSS 5 6 7 8 9 10 11 Sampling Switch (kΩ) See Section 17.0 “Electrical Specifications”.
PIC16F882/883/884/886/887 TABLE 9-2: Name SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ADCON1 ADFM — VCFG1 VCFG0 — — — — 0-00 ---- -000 ---- ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 --11 1111 --11 1111 ANSELH ADRESH A/D Result Register Hig
PIC16F882/883/884/886/887 NOTES: DS41291F-page 110 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 10.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs).
PIC16F882/883/884/886/887 REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EEDAT<7:0>: 8 Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory REGISTER 10-2: EEADR: EEPRO
PIC16F882/883/884/886/887 REGISTER 10-5: EECON1: EEPROM CONTROL REGISTER R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEP
PIC16F882/883/884/886/887 10.1.2 READING THE DATA EEPROM MEMORY 10.1.3 WRITING TO THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDAT register; therefore, it can be read in the next instruction. EEDAT will hold this value until another read or until it is written to by the user (during a write operation).
PIC16F882/883/884/886/887 10.1.4 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must write the Least and Most Significant address bits to the EEADR and EEADRH registers, set the EEPGD control bit of the EECON1 register, and then set control bit RD. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored.
PIC16F882/883/884/886/887 FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here EEADRH,EEADR INSTR (PC + 1) BSF EECON1,RD executed here PC +3 PC+3 EEDATH,EEDAT INSTR(PC + 1) executed here PC + 5 PC + 4 INSTR (PC + 3) Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDAT Register EE
PIC16F882/883/884/886/887 10.2 Writing to Flash Program Memory Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of the Configuration Word Register 2. Flash program memory must be written in eight-word blocks (four-word blocks for 4K memory devices). See Figures 10-2 and 10-3 for more details.
PIC16F882/883/884/886/887 FIGURE 10-2: BLOCK WRITES TO 2K AND 4K FLASH PROGRAM MEMORY 7 5 0 0 7 EEDATH Sixteen words of Flash are erased, then four buffers are transferred to Flash automatically after this word is written EEDATA 6 8 14 14 First word of block to be written 14 EEADR<1:0> = 00 EEADR<1:0> = 10 EEADR<1:0> = 01 Buffer Register Buffer Register 14 EEADR<1:0> = 11 Buffer Register Buffer Register Program Memory FIGURE 10-3: BLOCK WRITES TO 8K FLASH PROGRAM MEMORY 7 5 0 7 EEDATH
PIC16F882/883/884/886/887 An example of the complete eight-word write sequence is shown in Example 10-4. The initial address is loaded into the EEADRH and EEADR register pair; the eight words of data are loaded using indirect addressing.
PIC16F882/883/884/886/887 10.3 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 10-5) to the desired value to be written. EXAMPLE 10-5: WRITE VERIFY BANKSEL EEDAT MOVF EEDAT, W BANKSEL EECON1 BSF EECON1, RD BANKSEL XORWF BTFSS GOTO : BCF 10.3.
PIC16F882/883/884/886/887 TABLE 10-1: Name EECON1 EECON2 EEADR EEADRH EEDAT SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets EEPGD — — — WRERR WREN WR RD x--- x000 0--- q000 ---- ---- ---- ---- EEPROM Control Register 2 (not a physical register) EEADR7 EEADR6 EEADR5 EEADR4 — — — EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 EEADRH2 EEADRH1 EEADR
PIC16F882/883/884/886/887 NOTES: DS41291F-page 122 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 11.0 CAPTURE/COMPARE/PWM MODULES (CCP1 AND CCP2) This device contains one Enhanced Capture/Compare/ PWM (CCP1) and Capture/Compare/PWM module (CCP2). The CCP1 and CCP2 modules are identical in operation, with the exception of the Enhanced PWM features available on CCP1 only. See Section 11.6 “PWM (Enhanced Mode)” for more information. Note: CCPRx and CCPx throughout this document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 11.1 Enhanced Capture/Compare/PWM (CCP1) TABLE 11-1: The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle.
PIC16F882/883/884/886/887 11.2 Capture/Compare/PWM (CCP2) TABLE 11-2: The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle.
PIC16F882/883/884/886/887 11.3 11.3.2 Capture Mode In Capture mode, the CCPRxH, CCPRxL register pair captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set.
PIC16F882/883/884/886/887 11.4 11.4.2 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCPx module may: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt All Compare modes can generate an interrupt.
PIC16F882/883/884/886/887 11.5 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: • • • • PR2 T2CON CCPRxL CCPxCON FIGURE 11-4: CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCPx pin.
PIC16F882/883/884/886/887 11.5.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1. EQUATION 11-1: PWM PERIOD PWM Period = [ ( PR2 ) + 1 ] • 4 • T OSC • (TMR2 Prescale Value) Note: TOSC = 1/FOSC 11.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register.
PIC16F882/883/884/886/887 11.5.3 PWM RESOLUTION EQUATION 11-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 11-4.
PIC16F882/883/884/886/887 11.5.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 11.5.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 4.
PIC16F882/883/884/886/887 11.6 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution.
PIC16F882/883/884/886/887 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC
PIC16F882/883/884/886/887 FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) 10 (Half-Bridge) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1
PIC16F882/883/884/886/887 11.6.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-9). This mode can be used for Half-Bridge applications, as shown in Figure 11-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC16F882/883/884/886/887 11.6.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 11-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 11-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 11-11.
PIC16F882/883/884/886/887 FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high. © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 11.6.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register.
PIC16F882/883/884/886/887 FIGURE 11-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver. © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 11.6.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).
PIC16F882/883/884/886/887 11.6.4 ENHANCED PWM AUTOSHUTDOWN MODE A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state.
PIC16F882/883/884/886/887 REGISTER 11-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are
PIC16F882/883/884/886/887 FIGURE 11-15: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) Shutdown Event ECCPASE bit PWM Activity PWM Period ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes Start of PWM Period 11.6.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register.
PIC16F882/883/884/886/887 11.6.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 11-17: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC16F882/883/884/886/887 REGISTER 11-4: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts au
PIC16F882/883/884/886/887 11.6.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins.
PIC16F882/883/884/886/887 FIGURE 11-19: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal CCP1M1 1 PORT Data 0 P1A pin STRB CCP1M0 1 PORT Data 0 CCP1M1 1 PORT Data 0 P1C pin TRIS STRD PORT Data P1B pin TRIS STRC CCP1M0 TRIS P1D pin 1 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> = 00 and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 11.6.7.1 Steering Synchronization The STRSYNC bit of the PSTRCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1 pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
PIC16F882/883/884/886/887 TABLE 11-6: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP2CON — — DC2B1 DC2B0 CCP2M3 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Bit 2 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx xxxx xxxx CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx x
PIC16F882/883/884/886/887 NOTES: DS41291F-page 150 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 12.
PIC16F882/883/884/886/887 FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGH SPBRG Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register FIFO 8 Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control
PIC16F882/883/884/886/887 12.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16F882/883/884/886/887 12.1.1.4 TSR Status 12.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 12.1.1.5 1. 2. 3.
PIC16F882/883/884/886/887 TABLE 12-1: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 BAUDCTL ABDOVF INTCON PIE1 PIR1 RCREG Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 000
PIC16F882/883/884/886/887 12.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 12-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16F882/883/884/886/887 12.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16F882/883/884/886/887 12.1.2.8 1. 2. 3. 4. 5. 6. 7. 8. 9. Asynchronous Reception Set-up: 12.1.2.9 Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 12.3 “EUSART Baud Rate Generator (BRG)”). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register.
PIC16F882/883/884/886/887 TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 BAUDCTL ABDOVF GIE INTCON PIE1 PIR1 RCREG Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 RBIE T0IF INTF RBIF 0000 000x 0000 000x TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 0000 0000 0000 0000 Bit 5 Bit 4 Bit 3 RCIDL — SCKP PEIE T0IE INTE — ADI
PIC16F882/883/884/886/887 12.2 Clock Accuracy with Asynchronous Operation The factory calibrates the Internal Oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 12-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
PIC16F882/883/884/886/887 REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Rese
PIC16F882/883/884/886/887 REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit
PIC16F882/883/884/886/887 12.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCTL register selects 16-bit mode. If the system clock is changed during an active receive operation, a receive error or data loss may result.
PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103 2400 2404 0.
PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 — 1202 — 0.16 — 103 300 1202 0.16 0.16 207 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.
PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 300.0 1200 0.00 -0.02 6666 1666 2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.
PIC16F882/883/884/886/887 12.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 12.3.2 “Auto-Wake-up on Break”).
PIC16F882/883/884/886/887 12.3.2 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCTL register.
PIC16F882/883/884/886/887 FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: 12.3.3 If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks.
PIC16F882/883/884/886/887 FIGURE 12-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit) DS41291F-page 170 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 12.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16F882/883/884/886/887 FIGURE 12-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
PIC16F882/883/884/886/887 12.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16F882/883/884/886/887 FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16F882/883/884/886/887 12.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16F882/883/884/886/887 12.4.2.3 EUSART Synchronous Slave Reception 12.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 12.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16F882/883/884/886/887 12.5 EUSART Operation During Sleep The EUSART WILL remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 12.5.
PIC16F882/883/884/886/887 NOTES: DS41291F-page 178 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 13.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 13.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F882/883/884/886/887 REGISTER 13-1: SSPSTAT: SSP STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI i
PIC16F882/883/884/886/887 REGISTER 13-2: SSPCON: SSP CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmis
PIC16F882/883/884/886/887 REGISTER 13-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General cal
PIC16F882/883/884/886/887 13.3 SPI Mode FIGURE 13-1: The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported.
PIC16F882/883/884/886/887 When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The buffer full bit BF of the SSPSTAT register indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter.
PIC16F882/883/884/886/887 13.3.3 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. This, then, would give waveforms for SPI communication as shown in Figure 13-2, Figure 13-4 and Figure 13-5, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK.
PIC16F882/883/884/886/887 13.3.4 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit of the PIR1 register is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
PIC16F882/883/884/886/887 FIGURE 13-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Required SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 7 bit 5 bit 4 bit 3 bi
PIC16F882/883/884/886/887 13.3.6 SLEEP OPERATION 13.3.8 In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 13-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 13-1: In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device.
PIC16F882/883/884/886/887 13.4 MSSP I2C Operation The MSSP module in I 2C mode, fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware, to determine a free bus (Multi-Master mode). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer.
PIC16F882/883/884/886/887 13.4.1.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16F882/883/884/886/887 I 2C™ SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 13-7: Receiving Address R/W = 0 Receiving Data Receiving Data Not ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL 1 S 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SSPIF P Bus Master Terminates Transfer BF Cleared in software SSPBUF register is read SSPOV Bit SSPOV is set because the SSPBUF register is still full ACK is not sent I 2C™ S
PIC16F882/883/884/886/887 13.4.2 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that, the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices.
PIC16F882/883/884/886/887 MASTER MODE 13.4.4 Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle, with both the S and P bits clear. Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit.
PIC16F882/883/884/886/887 13.4.4.1 I2C™ Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC16F882/883/884/886/887 13.4.5 BAUD RATE GENERATOR In I2C Master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 13-11). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC16F882/883/884/886/887 13.4.6 I2C™ MASTER MODE START CONDITION TIMING 13.4.6.1 If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a Start condition, the user sets the Start Condition Enable bit SEN of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC16F882/883/884/886/887 13.4.7 I2C™ MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2 register) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
PIC16F882/883/884/886/887 13.4.8 I2C™ MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification, parameter 106).
© 2009 Microchip Technology Inc. R/W PEN SEN BF SSPIF SCL SDA S A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware.
DS41291F-page 200 S ACKEN SSPOV BF SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 2 4 5 6 Cleared in software 3 7 8 9 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 8 Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK P Bus Master terminates transfer Set P bit (SSPSTAT<4>) and SSPIF Set SSPIF interrupt at end of Acknowledge sequence PEN bit = 1 written here SSPOV is set because
PIC16F882/883/884/886/887 13.4.10 ACKNOWLEDGE SEQUENCE TIMING 13.4.11 An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2 register). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge Data bit (ACKDT) is presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence.
PIC16F882/883/884/886/887 FIGURE 13-18: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high, P bit (SSPSTAT) is set Write to SSPCON2 Set PEN PEN bit (SSPCON2) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. 13.4.12 CLOCK ARBITRATION 13.4.
PIC16F882/883/884/886/887 13.4.15 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT register) is set, or the bus is idle with both the S and P bits clear.
PIC16F882/883/884/886/887 13.4.16.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the Start condition (Figure 13-21). SCL is sampled low before SDA is asserted low (Figure 13-22).
PIC16F882/883/884/886/887 FIGURE 13-22: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, Bus collision occurs, set BCLIF SEN SCL =0 before BRG time-out, Bus collision occurs, set BCLIF BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 13-23: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled lo
PIC16F882/883/884/886/887 13.4.16.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e, another master is attempting to transmit a data ‘0’, see Figure 13-24). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from highto-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC16F882/883/884/886/887 13.4.16.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 13-26).
PIC16F882/883/884/886/887 13.4.17 SSP MASK REGISTER 2 An SSP Mask (SSPMSK) register is available in I C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit in the SSPSR register a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value.
PIC16F882/883/884/886/887 14.0 SPECIAL FEATURES OF THE CPU The PIC16F882/883/884/886/887 have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection.
PIC16F882/883/884/886/887 14.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 14-1. These bits are mapped in program memory location 2007h and 2008h, respectively. REGISTER 14-1: — Note: Address 2007h and 2008h are beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming.
PIC16F882/883/884/886/887 REGISTER 14-2: — CONFIG2: CONFIGURATION WORD REGISTER 2 — — — — WRT1 WRT0 BOR4V bit 15 bit 8 — — — — — — — — bit 7 bit 0 bit 15-11 Unimplemented: Read as ‘1’ bit 10-9 WRT<1:0>: Flash Program Memory Self Write Enable bits PIC16F883/PIC16F884 00 = 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by EECON control 01 = 0000h to 03FFh write protected, 0400h to 0FFFh may be modified by EECON control 10 = 0000h to 00FFh write protected, 0100h to 0FFFh
PIC16F882/883/884/886/887 14.2 Reset The PIC16F882/883/884/886/887 between various kinds of Reset: a) b) c) d) e) f) differentiates Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
PIC16F882/883/884/886/887 14.2.1 POWER-ON RESET (POR) FIGURE 14-2: The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See Section 17.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 14.2.4 “Brown-out Reset (BOR)”).
PIC16F882/883/884/886/887 14.2.4 BROWN-OUT RESET (BOR) occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOR for less than parameter (TBOR). The BOREN0 and BOREN1 bits in the Configuration Word Register 1 select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit (PCON<4>) enables/disables the BOR allowing it to be controlled in software.
PIC16F882/883/884/886/887 14.2.5 TIME-OUT SEQUENCE 14.2.6 On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figures 14-4, 14-5 and 14-6 depict time-out sequences.
PIC16F882/883/884/886/887 FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 14-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41291F-page 216 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 TABLE 14-4: Register W INDF TMR0 INITIALIZATION CONDITION FOR REGISTER Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu 00h/80h/10 0h/180h xxxx xxxx xxxx xxxx uuuu uuuu 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/10 2h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/10 3h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/8
PIC16F882/883/884/886/887 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED) Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) CCPR2H 1Ch xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 00-0 0000 00-0 0000 uu-u uuuu Register OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu TRIS
PIC16F882/883/884/886/887 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED) Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) CM2CON1 109h 0000 0--0 0000 0--0 uuuu u--u EEDAT 10Ch 0000 0000 0000 0000 uuuu uuuu EEADR 10Dh 0000 0000 0000 0000 uuuu uuuu EEDATH 10Eh --00 0000 --00 0000 --uu uuuu EEADRH 10Fh ---0 0000 ---0 0000 ---u uuuu SRCON 185h 0000 00
PIC16F882/883/884/886/887 14.
PIC16F882/883/884/886/887 14.3.2 TIMER0 INTERRUPT 14.3.3 An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. An input change on PORTB change sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<3>) bit. Plus, individual pins can be configured through the IOCB register.
PIC16F882/883/884/886/887 FIGURE 14-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON<1>) Interrupt Latency (2) (5) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched INTCON Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) — Dummy Cycle Inst (PC) 0005h INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY.
PIC16F882/883/884/886/887 14.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the upper 16 bytes of all GPR banks are common in the PIC16F882/883/884/886/887 (see Figures 2-2 and 2-3), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here.
PIC16F882/883/884/886/887 14.5 14.5.2 Watchdog Timer (WDT) The WDT has the following features: • • • • • Operates from the LFINTOSC (31 kHz) Contains a 16-bit prescaler Shares an 8-bit prescaler with Timer0 Time-out period is from 1 ms to 268 seconds Configuration bit and software controlled WDT is cleared under certain conditions described in Table 14-7. 14.5.1 WDT OSCILLATOR The WDT derives its time base from the 31 kHz LFINTOSC.
PIC16F882/883/884/886/887 REGISTER 14-3: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 =
PIC16F882/883/884/886/887 14.6 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance).
PIC16F882/883/884/886/887 FIGURE 14-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (3) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 14.7 Processor in Sleep PC Inst(PC) = Sleep Inst(PC – 1) PC + 1 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) 14.
PIC16F882/883/884/886/887 FIGURE 14-11: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING™ CONNECTION To Normal Connections External Connector Signals PIC16F882/883/ 884/886/887 * +5V VDD 0V VSS VPP RE3/MCLR/VPP CLK RB6 Data I/O RB7 * * * To Normal Connections * Isolation devices (as required) 14.10 Low-Voltage (Single-Supply) ICSP Programming The LVP bit of the Configuration Word enables low-voltage ICSP programming.
PIC16F882/883/884/886/887 For more information, see “Using MPLAB® ICD 2” (DS51265), available on Microchip’s web site (www.microchip.com). 14.11 In-Circuit Debugger The PIC16F882/883/884/886/887-ICD can be used in any of the package types. The device will be mounted on the target application board, which in turn has a 3 or 4 wire connection to the ICD tool. 14.11.1 ICD PINOUT The devices in the PIC16F88X family carry the circuitry for the In-Circuit Debugger on-chip and on existing device pins.
PIC16F882/883/884/886/887 NOTES: DS41291F-page 230 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 15.
PIC16F882/883/884/886/887 TABLE 15-2: PIC16F882/883/884/886/887 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 I
PIC16F882/883/884/886/887 15.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16F882/883/884/886/887 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16F882/883/884/886/887 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F882/883/884/886/887 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) f Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself.
PIC16F882/883/884/886/887 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16F882/883/884/886/887 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F882/883/884/886/887 SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Operation: (W) .XOR. (f) → (destination) Status Affected: C, DC, Z Status Affected: Z Description: Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC16F882/883/884/886/887 NOTES: DS41291F-page 240 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 16.
PIC16F882/883/884/886/887 16.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC16F882/883/884/886/887 16.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F882/883/884/886/887 16.11 PICSTART Plus Development Programmer 16.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC16F882/883/884/886/887 17.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ..................................................................................
PIC16F882/883/884/886/887 FIGURE 17-1: PIC16F883/884/886/887 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 17-2: 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41291F-page 246 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 17.1 DC Characteristics: PIC16F883/884/886/887-I (Industrial) PIC16F883/884/886/887-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Min. Typ† Max. Units Sym. Characteristic Conditions VDD Supply Voltage 2.0 2.0 3.0 4.5 — — — — 5.5 5.5 5.5 5.
PIC16F882/883/884/886/887 17.2 DC Characteristics: PIC16F883/884/886/887-I (Industrial) PIC16F883/884/886/887-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. D010 Conditions Device Characteristics Min. Typ† Max. Units VDD Supply Current (IDD) D011* D012 D013* D014 D015 D016* D017 D018 D019 (1, 2) — 13 19 μA 2.0 — 22 30 μA 3.
PIC16F882/883/884/886/887 17.3 DC Characteristics: PIC16F883/884/886/887-I (Industrial) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Device Characteristics Power-down Base Current(IPD)(2) D021 Min. Typ† Max. Units VDD Note WDT, BOR, Comparators, VREF and T1OSC disabled — 0.05 1.2 μA 2.0 — 0.15 1.5 μA 3.0 — 0.35 1.8 μA 5.0 — 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C — 1.
PIC16F882/883/884/886/887 17.4 DC Characteristics: PIC16F883/884/886/887-E (Extended) DC CHARACTERISTICS Param No. D020E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2) D021E D022E D023E D024E D025E* D026E D027E D028E Min. Typ† Max. Units VDD Note WDT, BOR, Comparators, VREF and T1OSC disabled — 0.05 9 μA 2.0 — 0.15 11 μA 3.0 — 0.35 15 μA 5.
PIC16F882/883/884/886/887 17.5 DC Characteristics: PIC16F883/884/886/887-I (Industrial) PIC16F883/884/886/887-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym. VIL Characteristic Min. Typ† Max. Units Vss Vss Conditions — 0.8 V 4.5V ≤ VDD ≤ 5.5V — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.
PIC16F882/883/884/886/887 17.5 DC Characteristics: PIC16F883/884/886/887-I (Industrial) PIC16F883/884/886/887-E (Extended) (Continued) DC CHARACTERISTICS Param No. Sym. D100 IULP Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min. Typ† Max.
PIC16F882/883/884/886/887 17.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Typ. Units TH01 θJA Thermal Resistance Junction to Ambient 47.2 24.4 45.8 60.2 80.2 89.4 29 C/W C/W C/W C/W C/W C/W C/W TH02 θJC Thermal Resistance Junction to Case 24.7 20.0 14.5 29 23.8 23.9 20.
PIC16F882/883/884/886/887 17.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16F882/883/884/886/887 17.8 AC Characteristics: PIC16F883/884/886/887 (Industrial, Extended) FIGURE 17-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 17-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. OS01 Sym.
PIC16F882/883/884/886/887 TABLE 17-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) — — — 2 TOSC Slowest clock OS07 TSC Fail-Safe Sample Clock Period(1) — — 21 — ms LFINTOSC/64 OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.
PIC16F882/883/884/886/887 FIGURE 17-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 17-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Min. Typ† Max.
PIC16F882/883/884/886/887 FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
PIC16F882/883/884/886/887 TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Min. Typ† Max.
PIC16F882/883/884/886/887 FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. 40* Sym.
PIC16F882/883/884/886/887 FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: TABLE 17-6: Refer to Figure 17-3 for load conditions. CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. CC01* CC02* CC03* Sym. TccL TccH TccP Characteristic CCP1 Input Low Time CCP1 Input High Time CCP1 Input Period Min. Typ† Max. Units No Prescaler 0.
PIC16F882/883/884/886/887 TABLE 17-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristics CM01 VOS Input Offset Voltage CM02 VCM Input Common Mode Voltage CM03* CMRR Common Mode Rejection Ratio CM04* TRT Response Time Min. Typ† Max. Units — ± 5.0 ± 10 mV 0 — VDD - 1.
PIC16F882/883/884/886/887 TABLE 17-10: PIC16F883/884/886/887 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 bits AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error 0 +1.5 +3.0 LSb VREF = 5.
PIC16F882/883/884/886/887 TABLE 17-11: PIC16F883/884/886/887 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym. No. AD130* TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min. Typ† 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.
PIC16F882/883/884/886/887 FIGURE 17-10: PIC16F883/884/886/887 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE Note 1: Sampling Stopped AD132 Sample If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16F882/883/884/886/887 FIGURE 17-12: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 17-3 for load conditions. TABLE 17-12: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param. No.
PIC16F882/883/884/886/887 FIGURE 17-14: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 17-3 for load conditions.
PIC16F882/883/884/886/887 FIGURE 17-16: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb bit 6 - - - - - -1 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 17-3 for load conditions. FIGURE 17-17: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 bit 6 - - - -1 LSb In 74 Note: Refer to Figure 17-3 for load conditions.
PIC16F882/883/884/886/887 TABLE 17-14: SPI MODE REQUIREMENTS Param No. Symbol 70* Characteristic TSSL2SCH, SS↓ to SCK↓ or SCK↑ input TSSL2SCL Min. Typ† Max.
PIC16F882/883/884/886/887 TABLE 17-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol 90* TSU:STA 91* THD:STA 92* TSU:STO 93 THD:STO Stop condition Characteristic Start condition 100 kHz mode 4700 Typ. Max. Units — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * Min.
PIC16F882/883/884/886/887 TABLE 17-16: I2C™ BUS DATA REQUIREMENTS Param. No. 100* Symbol THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC16F882/883/884/886/887 NOTES: DS41291F-page 272 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16F882/883/884/886/887 FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 6.0 5.0 5.5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5V 4.0 IDD (mA) 4V 3.0 3V 2.0 2V 1.0 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz VDD (V) FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) HS Mode 5.0 4.5 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5V 4.5V IDD (mA) 3.
PIC16F882/883/884/886/887 FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) HS Mode 5.5 5.0 4.5 4.0 5.5V 5V 4.5V Typical: Mean @25°C4V 3V Statistical 3.5V 4.5V 5V 5.5V Maximum: Mean (Worst-case Temp) + 3σ 0.8868608641.0693043161.2645617521.4868166111.5076394231.520959608 (-40°C1.6176371031.9623642592.3355493582.7630868222.8139211682.849632041 to 125°C) 3.8375797553.9157601913.967889512 4.685048474 4.78069621 IDD (mA) 3.5 3.0 2.5 4V 2.0 3.5V 3V 1.5 1.0 0.5 0.
PIC16F882/883/884/886/887 FIGURE 18-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,600 1,400 IDD (uA) 1,200 1,000 4 MHz 800 600 1 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.5 5.0 5.5 VDD (V) TYPICAL IDD vs.
PIC16F882/883/884/886/887 FIGURE 18-8: MAXIMUM IDD vs. VDD (EXTRC MODE) 2,000 Typical: Typical:Statistical StatisticalMean Mean@25°C @25×C Maximum:Mean Mean(Worst-case (Worst CaseTemp) Temp)+ +3σ3 Maximum: (-40×C to 125×C) (-40°C to 125°C) 1,800 1,600 1,400 4 Mhz IDD (uA) 1,200 1,000 800 1 Mhz 600 400 200 0 2.0 2.5 3.0 4.0 3.5 4.5 5.0 5.5 VDD (V) FIGURE 18-9: IDD vs.
PIC16F882/883/884/886/887 FIGURE 18-10: IDD vs. VDD (LP MODE) 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 70 IDD (uA) 60 50 32 kHz Maximum 40 30 32 kHz Typical 20 10 0 2.0 3.0 2.5 4.0 3.5 4.5 5.0 5.5 VDD (V) FIGURE 18-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) 4V 2,500 IDD (uA) 2,000 HFINTOSC 5V 5.5V 197.9192604299.82617395.019 496.999 574.901 210.9124688 324.4079 431.721 544.182 620.
PIC16F882/883/884/886/887 FIGURE 18-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 3,000 2,500 5.5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5V IDD (uA) 2,000 4V 1,500 3V 1,000 2V 500 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz VDD (V) FIGURE 18-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.
PIC16F882/883/884/886/887 FIGURE 18-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18 16 Typical: Statistical Mean @25°C Maximum: Mean + 3σ Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 14 Max. 125°C IPD (μA) 12 10 8 6 4 Max. 85°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-15: COMPARATOR IPD vs.
PIC16F882/883/884/886/887 FIGURE 18-16: BOR IPD vs. VDD OVER TEMPERATURE 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 120 IPD (μA) 100 Maximum 80 Typical 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-17: TYPICAL WDT IPD vs. VDD (25°C) 3.0 2.5 IPD (uA) 2.0 1.5 Typical:Typical Statistical Mean @25°C Max 125×C Max 85×C 2 1.007 2.140 27.702 2.5 1.146 2.711 29.079 3 1.285 3.282 30.08 3.5 1.449 3.899 31.347 4 1.612 4.515 32.238 4.
PIC16F882/883/884/886/887 FIGURE 18-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 40.0 Maximum: Mean +3 Maximum: Mean + 3σ 35.0 Max. 125°C 30.0 IPD (uA) 25.0 20.0 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-19: WDT PERIOD vs. VDD OVER TEMPERATURE WDT Time-out Period 32 30 Maximum: Mean + 3σ (-40°C to 125°C) 28 Max. (125°C) 26 Max. (85°C) Time (ms) 24 22 20 Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F882/883/884/886/887 FIGURE 18-20: WDT PERIOD vs. TEMPERATURE (VDD = 5.0V) Vdd = 5V 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 26 Maximum Time (ms) 24 22 20 Typical 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 18-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range IPD (uA) 140 Max 85×C Max 125×C 35.8 68.0 Mean @25°C Typical: Statistical 44.8 77.3 (Worst-case Temp) + 3σ Maximum: Mean 53.8 86.5 120 (-40°C to 125°C) 62.
PIC16F882/883/884/886/887 FIGURE 18-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) low Range 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 Max. 125°C IPD (uA) 120 100 Max. 85°C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.5 5.0 5.5 VDD (V) FIGURE 18-23: TYPICAL VP6 REFERENCE IPD vs. VDD (25°C) VP6 Reference IPD vs. VDD (25×C) 160 140 120 IPD (uA) 100 Typical 80 60 40 20 0 2.0 2.5 3.0 3.5 4.
PIC16F882/883/884/886/887 FIGURE 18-24: MAXIMUM VP6 REFERENCE IPD vs. VDD OVER TEMPERATURE Max VP6 Reference IPD vs. VDD Over Temperature 180 160 140 Max 125°C IPD (uA) 120 Max 85°C 100 80 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 18-25: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 30 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. 125°C IPD (uA) 20 15 10 5 2 2.5 3 3.5 4 4.5 5 5.5 Typ 25×C 2.022 2.247 2.472 2.
PIC16F882/883/884/886/887 FIGURE 18-26: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean + 3σ Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) FIGURE 18-27: 0.45 Typical: Statistical Mean @25°C Typical: Statistical Maximum: Mean + 3σ Mean Maximum: Means + 3 0.40 Max. 125°C 0.
PIC16F882/883/884/886/887 FIGURE 18-28: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 18-29: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
PIC16F882/883/884/886/887 FIGURE 18-30: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-31: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.
PIC16F882/883/884/886/887 FIGURE 18-32: 4 5.5 COMPARATOR RESPONSE TIME (RISING EDGE) 200 278 639 846 V+ input 202 = VCM 531 140 V- input = Transition from VCM + 100MV to VCM - 20MV 1,000 900 800 Max. (125°C) Response Time (nS) 700 600 Note: 500 VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100MV to VCM - 20MV Max. (85°C) 400 300 Typ. (25°C) 200 Min. (-40°C) 100 0 2.0 2.5 4.0 5.
PIC16F882/883/884/886/887 FIGURE 18-34: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ. 25°C Frequency (Hz) 30,000 25,000 20,000 Min. 85°C Min. 125°C 15,000 10,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case) + 3σ 5,000 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-35: ADC CLOCK PERIOD vs.
PIC16F882/883/884/886/887 FIGURE 18-36: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case) + 3σ 14 85°C 12 25°C Time (μs) 10 -40°C 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-37: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case) + 3σ Time (μs) 20 15 85°C 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F882/883/884/886/887 FIGURE 18-38: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 8 7 Time (μs) 85°C 6 25°C 5 -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41291F-page 292 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 FIGURE 18-40: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-41: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 FIGURE 18-42: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-43: TYPICAL VP6 REFERENCE VOLTAGE vs. VDD (25°C) VP6 Reference Voltage vs. VDD (25×C) 0.65 0.64 0.63 VP6 (V) 0.62 0.61 0.60 0.59 Typical 0.58 0.57 0.56 0.55 2 3 4 5 5.5 VDD (V) DS41291F-page 294 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 FIGURE 18-44: VP6 DRIFT OVER TEMPERATURE NORMALIZED AT 25°C (VDD 5V) 4 Change from Nominal in % 3 2 1 0 -1 -2 -40 0 25 85 125 Temperature in Degrees C FIGURE 18-45: VP6 DRIFT OVER TEMPERATURE NORMALIZED AT 25°C (VDD 3V) 4 Change from Nominal in % 3 2 1 0 -1 -2 -40 0 25 85 125 Temperature in Degrees C © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 FIGURE 18-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 25×C) 35 Parts=118 Number of Parts 30 25 20 15 10 5 0.690 0.700 0.690 0.700 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
PIC16F882/883/884/886/887 FIGURE 18-48: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 125×C) 40 35 Parts=118 Number of Parts 30 25 20 15 10 5 0.700 0.690 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
PIC16F882/883/884/886/887 FIGURE 18-50: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 Number of Parts 25 Parts=118 20 15 10 5 0.700 0.690 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
PIC16F882/883/884/886/887 FIGURE 18-52: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 25 Number of Parts Parts=118 20 15 10 5 0.700 0.690 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
PIC16F882/883/884/886/887 NOTES: DS41291F-page 300 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 28-Lead PDIP Example XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F886/SO e3 0710017 Example 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead QFN PIC16F883 -I/SS e3 0710017 Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC16F882/883/884/886/887 19.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead QFN 44-Lead TQFP PIC16F887 -I/ML e3 0710017 Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC16F882/883/884/886/887 19.2 Package Details The following sections give the technical details of the packages. ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC16F882/883/884/886/887 # # $ % &'( # ) ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 L1 6 &! ' ! 9 ' &! 7"') % ! β 99 . . 7 7: 7 ; < & : 8 & = = = = = - # # 4 4 !! & # %% + 1 , : > #& .
PIC16F882/883/884/886/887 *+ ! " # (' # 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 1 2 b NOTE 1 e c A2 A φ A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = ? < & # %% = = : > #& . < < # # 4 > #& .
PIC16F882/883/884/886/887 , - % ! . / 010 ,-! 2 * '(( ) . * ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC16F882/883/884/886/887 , - % ! . / 010 ,-! 2 * '(( ) . * ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 3 0 ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; & & 7: 1 , = = = 1 ! & & = = .
PIC16F882/883/884/886/887 33 , - % ! . / 1 ,-! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; & : 8 & < & # %% , & & 4 !! - : > #& . .
PIC16F882/883/884/886/887 33 , - % ! . / 1 ,-! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS41291F-page 310 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 33 4* ! " , - 5 4 6 16 16 % ' 4,- 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β L A1 6 &! ' ! 9 ' &! 7"') % 9 #! A2 L1 99 . .
PIC16F882/883/884/886/887 33 4* ! " , - 5 4 6 16 16 % ' 4,- 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS41291F-page 312 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: Revision A (5/2006) MIGRATING FROM OTHER PIC® DEVICES Initial release of this data sheet. This discusses some of the issues in migrating from other PIC devices to the PIC16F88X Family of devices. Revision B (7/2006) B.1 Pin Diagrams (44-Pin QFN drawing); Revised Table 2-1, Addr. 1DH (CCP2CON); Section 3.0, 3.1; Section 3.4.4.6; Table 3; Table 3-1 (ANSEL); Table 3-3 (CCP2CON); Register 3-1; Register 3.
PIC16F882/883/884/886/887 NOTES: DS41291F-page 314 © 2009 Microchip Technology Inc.
PIC16F882/883/884/886/887 INDEX A A/D Specifications.................................................... 263, 264 Absolute Maximum Ratings .............................................. 245 AC Characteristics Industrial and Extended ............................................ 255 Load Conditions ........................................................ 254 ACKSTAT ......................................................................... 198 ACKSTAT Status Flag ...............................................
PIC16F882/883/884/886/887 Prescaler ................................................................... 126 PWM Mode ............................................................... 128 Duty Cycle......................................................... 129 Effects of Reset................................................. 131 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 130 Example PWM Frequencies and Resolutions, 8 MHz...................................
PIC16F882/883/884/886/887 EUSART ........................................................................... 151 Associated Registers Baud Rate Generator........................................ 163 Asynchronous Mode ................................................. 153 12-bit Break Transmit and Receive .................. 169 Associated Registers Receive..................................................... 159 Transmit.................................................... 155 Auto-Wake-up on Break ............
PIC16F882/883/884/886/887 RETURN ................................................................... 237 RLF ........................................................................... 238 RRF........................................................................... 238 SLEEP ...................................................................... 238 SUBLW ..................................................................... 238 SUBWF .....................................................................
PIC16F882/883/884/886/887 PORTA Register ................................................................. 39 PORTB................................................................................ 47 Additional Pin Functions ............................................. 47 ANSELH Register ............................................... 47 Weak Pull-up ...................................................... 47 Associated Registers .................................................. 52 Interrupt-on-Change.......
PIC16F882/883/884/886/887 SSPCON (MSSP Control 1)...................................... 181 SSPCON2 (SSP Control 2)....................................... 182 SSPMSK (SSP Mask) ............................................... 208 SSPSTAT (SSP Status) ............................................ 180 STATUS ...................................................................... 29 T1CON ........................................................................ 79 T2CON ............................................
PIC16F882/883/884/886/887 Bus Collision During a Stop Condition ...................... 207 Bus Collision for Transmit and Acknowledge............ 203 CLKOUT and I/O....................................................... 257 Clock Timing ............................................................. 255 Comparator Output ..................................................... 83 Enhanced Capture/Compare/PWM (ECCP) ............. 261 EUSART Synchronous Receive (Master/Slave) .......
PIC16F882/883/884/886/887 NOTES: DS41291F-page 322 © 2009 Microchip Technology Inc.
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PIC16F882/883/884/886/887 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F883(1), PIC16F883T(1, 2), PIC16F884(1), PIC16F884T(1, 2), PIC16F886(1), PIC16F886T(1, 2), PIC16F887(1), PIC16F887T(1, 2) VDD range 2.0V to 5.
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