Datasheet

 2006-2012 Microchip Technology Inc. DS41291G-page 273
PIC16F882/883/884/886/887
TABLE 17-14: SPI MODE REQUIREMENTS
FIGURE 17-18: I
2
C™ BUS START/STOP BITS TIMING
Param
No.
Symbol Characteristic Min. Typ† Max. Units Conditions
70* T
SSL2SCH,
T
SSL2SCL
SS
 to SCK or SCK input TCY ——ns
71* T
SCH SCK input high time (Slave mode) TCY + 20 — — ns
72* T
SCL SCK input low time (Slave mode) TCY + 20 — — ns
73* TDIV2SCH,
T
DIV2SCL
Setup time of SDI data input to SCK edge 100 — — ns
74* T
SCH2DIL,
T
SCL2DIL
Hold time of SDI data input to SCK edge 100 — — ns
75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns
2.0-5.5V — 25 50 ns
76* T
DOF SDO data output fall time — 10 25 ns
77* T
SSH2DOZSS to SDO output high-impedance 10 — 50 ns
78* TSCR SCK output rise time
(Master mode)
3.0-5.5V — 10 25 ns
2.0-5.5V — 25 50 ns
79* T
SCF SCK output fall time (Master mode) — 10 25 ns
80* TSCH2DOV,
T
SCL2DOV
SDO data output valid after
SCK edge
3.0-5.5V — — 50 ns
2.0-5.5V — — 145 ns
81* T
DOV2SCH,
T
DOV2SCL
SDO data output setup to SCK edge Tcy — — ns
82* T
SSL2DOV SDO data output valid after SS edge — — 50 ns
83* T
SCH2SSH,
T
SCL2SSH
SS
after SCK edge 1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note: Refer to Figure 17-3 for load conditions.
91
92
93
SCL
SDA
Start
Condition
Stop
Condition
90