Datasheet

PIC16F882/883/884/886/887
DS41291G-page 226  2006-2012 Microchip Technology Inc.
FIGURE 14-8: INT PIN INTERRUPT TIMING
TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 33
PIE1
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 34
PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 35
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 36
PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF
— CCP2IF 37
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1
PC + 1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC + 1)
Inst (PC – 1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 T
CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(2)
(3)
(4)
(5)
(1)