Datasheet

 2006-2012 Microchip Technology Inc. DS41291G-page 225
PIC16F882/883/884/886/887
14.3.2 TIMER0 INTERRUPT
An overflow (FFh  00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>)
bit. See Section 5.0 “Timer0 Module” for operation of
the Timer0 module.
14.3.3 PORTB INTERRUPT
An input change on PORTB change sets the RBIF
(INTCON<0>) bit. The interrupt can be
enabled/disabled by setting/clearing the RBIE
(INTCON<3>) bit. Plus, individual pins can be
configured through the IOCB register.
FIGURE 14-7: INTERRUPT LOGIC
Note: If a change on the I/O pin should occur
when the read operation is being
executed (start of the Q2 cycle), then the
RBIF interrupt flag may not get set. See
Section 3.4.3 “Interrupt-on-Change” for
more information.
C1IF
C1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
(1)
Interrupt to CPU
EEIE
EEIF
ADIF
ADIE
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2
IOCB2
IOC-RB3
IOCB3
CCP1IF
CCP1IE
OSFIF
OSFIE
C2IF
C2IE
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
RCIF
RCIE
TMR2IE
TMR2IF
SSPIE
SSPIF
TXIE
TXIF
TMR1IE
TMR1IF
Note 1: Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 14.6.1
“Wake-up from Sleep”.
BCLIE
BCLIF
ULPWUIF
ULPWUIE
CCP2IF
CCP2IE