Datasheet

PIC16F882/883/884/886/887
DS41291G-page 214  2006-2012 Microchip Technology Inc.
14.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 14-1.
These bits are mapped in program memory location
2007h and 2008h, respectively.
REGISTER DEFINITIONS: CONFIGURATION WORDS
Note: Address 2007h and 2008h are beyond the
user program memory space. It belongs to
the special configuration memory space
(2000h-3FFFh), which can be accessed
only during programming. See “PIC16F88X
Memory Programming Specification”
(DS41287) for more information.
REGISTER 14-1: CONFIG1: CONFIGURATION WORD REGISTER 1
DEBUG LVP FCMEN IESO BOREN<1:0>
bit 13 bit 8
CPD
CP MCLRE PWRTE WDTE FOSC<2:0>
bit 7 bit 0
bit 13 DEBUG
: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
bit 12 LVP: Low Voltage Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 pin is digital I/O, HV on MCLR
must be used for programming
bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10 IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits
(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 7 CPD
: Data Code Protection bit
(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 6 CP
: Code Protection bit
(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: RE3/MCLR
pin function select bit
(4)
1 = RE3/MCLR pin function is MCLR
0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR
is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.