Datasheet

 2006-2012 Microchip Technology Inc. DS41291G-page 159
PIC16F882/883/884/886/887
FIGURE 12-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCTL
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 33
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 34
PIR1
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 36
RCREG EUSART Receive Data Register 162
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 165
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 167
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 167
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 55
TXREG
EUSART Transmit Data Register 157
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 164
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)