PIC16F87/88 Data Sheet 18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F87/88 18/20/28-Pin Enhanced Flash MCUs with nanoWatt Technology Low-Power Features: Pin Diagram • Power-Managed modes: - Primary Run: RC oscillator, 76 µA, 1 MHz, 2V - RC_RUN: 7 µA, 31.25 kHz, 2V - SEC_RUN: 9 µA, 32 kHz, 2V - Sleep: 0.1 µA, 2V • Timer1 Oscillator: 1.8 µA, 32 kHz, 2V • Watchdog Timer: 2.
PIC16F87/88 Pin Diagrams 18-Pin PDIP, SOIC 1 18 RA1/AN1 2 17 RA0/AN0 RA4/T0CKI/C2OUT RA5/MCLR/VPP 3 16 RA7/OSC1/CLKI 15 RA6/OSC2/CLKO VSS 5 14 VDD RB0/INT/CCP1(1) 6 13 RB7/PGD/T1OSI RB1/SDI/SDA 7 12 RB6/PGC/T1OSO/T1CKI RB2/SDO/RX/DT 8 11 RB5/SS/TX/CK RB3/PGM/CCP1(1) 9 10 RB4/SCK/SCL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD VDD RB7/PGD/T1OSI RB6/PGC/T1OSO/T1CKI RB5/SS/TX/CK RB4/SCK/SCL 4 PIC16F87 RA2/AN2/CVREF RA3/
PIC16F87/88 RA1/AN1 RA0/AN0 NC 23 22 25 24 RA2/AN2/CVREF NC 26 RA4/T0CKI/C2OUT RA3/AN3/C1OUT 27 28-Pin QFN 28 Pin Diagrams (Cont’d) RA5/MCLR/VPP 1 21 RA7/OSC1/CLKI NC VSS 2 20 RA6/OSC2/CLKO 3 19 VDD NC 4 18 NC VSS 5 17 VDD NC 6 16 RB7/PGD/T1OSI RB0/INT/CCP1(1) 7 15 RB6/PGC/T1OSO/T1CKI 14 NC 22 NC 13 12 RB4/SCK/SCL RB5/SS/TX/CK RA1/AN1 RA0/AN0 23 11 NC 24 10 RB3/PGM/CCP1(1) RA2/AN2/CVREF/VREF- NC 25 9 26 8 RB1/SDI/SDA 27 RB2/SDO/RX/DT RA4/AN4/T0CKI
PIC16F87/88 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................. 11 3.0 Data EEPROM and Flash Program Memory............................................................
PIC16F87/88 1.0 DEVICE OVERVIEW This document contains device specific information for the operation of the PIC16F87/88 devices. Additional information may be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023) which may be downloaded from the Microchip web site. This Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
PIC16F87/88 FIGURE 1-1: PIC16F87 DEVICE BLOCK DIAGRAM 13 Program Memory Program Bus 14 RAM Addr(1) RA0/AN0 RA1/AN1 RA2/AN2/CVREF RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/VPP RA6/OSC2/CLKO RA7/OSC1/CLKI 9 PORTB Addr MUX Instruction reg 7 Direct Addr PORTA RAM File Registers 368 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter Flash 8 Indirect Addr FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Tim
PIC16F87/88 FIGURE 1-2: PIC16F88 DEVICE BLOCK DIAGRAM 13 Program Memory Program Bus 14 RAM Addr(1) RA0/AN0 RA1/AN1 RA2/AN2/CVREF/VREFRA3/AN3/VREF+/C1OUT RA4/AN4/T0CKI/C2OUT RA5/MCLR/VPP RA6/OSC2/CLKO RA7/OSC1/CLKI 9 PORTB Addr MUX Instruction reg 7 Direct Addr PORTA RAM File Registers 368 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter Flash 8 RB0/INT/CCP1(2) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(2) RB4/SCK/SCL RB5/SS/TX/CK RB6/AN5/PGC/T1OSO/T1CKI RB7/AN6/PGD/T1OSI Indire
PIC16F87/88 TABLE 1-2: PIC16F87/88 PINOUT DESCRIPTION PDIP/ SOIC Pin# SSOP Pin# QFN Pin# RA0/AN0 RA0 AN0 17 19 23 RA1/AN1 RA1 AN1 18 RA2/AN2/CVREF/VREFRA2 AN2 CVREF VREF-(4) 1 RA3/AN3/VREF+/C1OUT RA3 AN3 VREF+(4) C1OUT 2 RA4/AN4/T0CKI/C2OUT RA4 AN4(4) T0CKI C2OUT 3 RA5/MCLR/VPP RA5 MCLR 4 Pin Name I/O/P Type Buffer Type Description PORTA is a bidirectional I/O port. 20 1 2 3 4 15 17 Legend: Note 1: 2: 3: 4: 5: 16 18 Bidirectional I/O pin. Analog input channel 0.
PIC16F87/88 TABLE 1-2: PIC16F87/88 PINOUT DESCRIPTION (CONTINUED) Pin Name PDIP/ SOIC Pin# SSOP Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
PIC16F87/88 NOTES: DS30487C-page 10 2005 Microchip Technology Inc.
PIC16F87/88 2.0 MEMORY ORGANIZATION FIGURE 2-1: There are two memory blocks in the PIC16F87/88 devices. These are the program memory and the data memory. Each block has its own bus, so access to each block can occur during the same oscillator cycle. PC<12:0> CALL, RETURN RETFIE, RETLW The data memory can be further broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here.
PIC16F87/88 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly, through the File Select Register (FSR). FIGURE 2-2: PIC16F87 REGISTER FILE MAP Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh Indirect addr.
PIC16F87/88 FIGURE 2-3: PIC16F88 REGISTER FILE MAP File Address File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.
PIC16F87/88 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1: Address The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
PIC16F87/88 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page 0000 0000 26, 135 1111 1111 18, 69 0000 0000 135 Bank 1 80h(2) INDF 81h OPTION_REG 82h(2) PCL 83h(2) STATUS (2) Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter (PC) Least Significant Byte 84h FSR 85h TRISA
PIC16F87/88 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on: POR, BOR Details on page Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 26, 135 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 2 100h(2) INDF 101h TMR0 Timer0 Module Register xxxx xxxx 69 102h(2) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 135 103h(2) STATUS 104h(2) FSR 105h WDTCON 106h PORTB IRP RP1
PIC16F87/88 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F87/88 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register is a readable and writable register that contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F87/88 2.2.2.3 INTCON Register The INTCON register is a readable and writable register that contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F87/88 2.2.2.4 PIE1 Register This register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16F87/88 2.2.2.5 PIR1 Register This register contains the individual flag bits for the peripheral interrupts. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F87/88 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt.
PIC16F87/88 2.2.2.7 PIR2 Register The PIR2 register contains the flag bit for the EEPROM write operation interrupt. . Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F87/88 2.2.2.8 Note: PCON Register Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR), a Brown-out Reset, an external MCLR Reset and WDT Reset.
PIC16F87/88 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register which is a readable and writable register. The upper bits (PC<12:8>) are not readable but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will be cleared. Figure 2-4 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F87/88 2.5 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-2: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR.
PIC16F87/88 3.0 DATA EEPROM AND FLASH PROGRAM MEMORY The data EEPROM and Flash program memory are readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers.
PIC16F87/88 REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch) R/W-x U-0 U-0 R/W-x R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-5 Unimplemented: Read as ‘0’ bit 4 FREE: EEPROM Forced Row Erase bit 1 = Erase the program memory row addressed by EEADRH:EEADR on the next WR command 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit 1 =
PIC16F87/88 3.3 Reading Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The data is available in the very next cycle in the EEDATA register; therefore, it can be read in the next instruction (see Example 3-1). EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
PIC16F87/88 3.5 Reading Flash Program Memory To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored.
PIC16F87/88 EXAMPLE 3-4: ERASING A FLASH PROGRAM MEMORY ROW BANKSEL MOVF MOVWF MOVF MOVWF EEADRH ADDRH, W EEADRH ADDRL, W EEADR ; Select Bank of EEADRH ; ; MS Byte of Program Address to Erase ; ; LS Byte of Program Address to Erase BANKSEL BSF BSF BSF EECON1 EECON1, EEPGD EECON1, WREN EECON1, FREE ; ; ; ; Select Bank of EECON1 Point to PROGRAM memory Enable Write to memory Enable Row Erase operation BCF MOVLW MOVWF MOVLW MOVWF BSF NOP INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR ; ; ; ; ; ; ; ; ;
PIC16F87/88 3.7 Writing to Flash Program Memory The user must follow the same specific sequence to initiate the write for each word in the program block by writing each program word in sequence (00, 01, 10, 11). Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT1:WRT0 of the device Configuration Word (Register 15-1). Flash program memory must be written in four-word blocks.
PIC16F87/88 An example of the complete four-word write sequence is shown in Example 3-5. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing, assuming that a row erase sequence has already been performed. EXAMPLE 3-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; ; ; ; ; ; 1. 2. 3. 4. 5. 6. The 32 words in the erase block have already been erased.
PIC16F87/88 3.8 Protection Against Spurious Write 3.9 There are conditions when the device should not write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents an EEPROM write. When the data EEPROM is code-protected, the microcontroller can read and write to the EEPROM normally. However, all external access to the EEPROM is disabled.
PIC16F87/88 4.0 OSCILLATOR CONFIGURATIONS 4.1 Oscillator Types TABLE 4-1: The PIC16F87/88 can be operated in eight different oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these eight modes (modes 5-8 are new PIC16 oscillator configurations): 1. 2. 3. 4. LP XT HS RC 5. RCIO 6. INTIO1 7. INTIO2 8. ECIO 4.
PIC16F87/88 FIGURE 4-2: CERAMIC RESONATOR OPERATION (HS OR XT OSC CONFIGURATION) OSC1 PIC16F87/88 (1) C1 RES RF(3) Sleep OSC2 C2(1) RS(2) To Internal Logic 4.3 External Clock Input The ECIO Oscillator mode requires an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset, or after an exit from Sleep mode. In the ECIO Oscillator mode, the OSC2 pin becomes an additional general purpose I/O pin.
PIC16F87/88 4.4 RC Oscillator 4.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation.
PIC16F87/88 4.5.1 INTRC MODES 4.5.2 Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, after which it can be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.
PIC16F87/88 4.6 Clock Sources and Oscillator Switching The PIC16F87/88 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC16F87/88 devices offer three alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes. FOSC2:FOSC0 configuration bits in Configuration Word 1 register.
PIC16F87/88 4.6.3 CLOCK TRANSITION AND WDT When clock switching is performed, the Watchdog Timer is disabled because the Watchdog ripple counter is used as the Oscillator Start-up Timer. Note: Once the clock transition is complete (i.e., new oscillator selection switch has occurred), the Watchdog counter is re-enabled with the counter reset. This allows the user to synchronize the Watchdog Timer to the start of execution at the new clock frequency.
PIC16F87/88 FIGURE 4-6: PIC16F87/88 CLOCK DIAGRAM Configuration Word 1 (FOSC2:FOSC0) SCS<1:0> (T1OSC) Primary Oscillator OSC2 Sleep Secondary Oscillator T1OSC T1OSO To Timer1 T1OSCEN Enable Oscillator OSCCON<6:4> 8 MHz 4 MHz Internal Oscillator Block 8 MHz (INTOSC) 31.25 kHz (INTRC) 4.6.4 Internal Oscillator CPU 111 110 2 MHz Postscaler 31.25 kHz Source Peripherals MODIFYING THE IRCF BITS 101 1 MHz 100 500 kHz 250 kHz 125 kHz 31.
PIC16F87/88 4.6.6 • Clock before switch: One of INTOSC/INTOSC postscaler (IRCF<2:0> ≠ 000) 1. IRCF bits are modified to a different INTOSC/ INTOSC postscaler frequency. 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO is held low. 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it switches CLKO to this new clock source. 4. The IOFS bit is set. 5. Oscillator switchover is complete.
PIC16F87/88 4.7 Power-Managed Modes 4.7.1 If the system clock does not come from the INTRC (31.25 kHz) when the SCS bits are changed and the IRCF bits in the OSCCON register are configured for a frequency other than INTRC, the frequency may not be stable immediately. The IOFS bit (OSCCON<2>) will be set when the INTOSC or postscaler frequency is stable, after 4 ms (approx.).
PIC16F87/88 4.7.2 SEC_RUN MODE The core and peripherals can be configured to be clocked by T1OSC using a 32.768 kHz crystal. The crystal must be connected to the T1OSO and T1OSI pins. This is the same configuration as the low-power timer circuit (see Section 7.6 “Timer1 Oscillator”). When SCS bits are configured to run from T1OSC, a clock transition is generated.
PIC16F87/88 4.7.3 SEC_RUN/RC_RUN TO PRIMARY CLOCK SOURCE When switching from a SEC_RUN or RC_RUN mode back to the primary system clock, following a change of SCS<1:0> to ‘00’, the sequence of events that takes place will depend upon the value of the FOSC bits in the Configuration register. If the primary clock source is configured as a crystal (HS, XT or LP), then the transition will take place after 1024 clock cycles.
PIC16F87/88 FIGURE 4-9: TIMING FOR TRANSITION BETWEEN SEC_RUN/RC_RUN AND PRIMARY CLOCK Q4 Q1 Q2 Q3 Q4 TT1P(1) or TINP(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Secondary Oscillator OSC1 TOST OSC2 TOSC(3) Primary Clock TSCS(4) System Clock TDLY(5) SCS<1:0> OSTS Program Counter Note 1: 2: 3: 4: 5: PC PC + 1 PC + 2 PC + 3 TT1P = 30.52 µs. TINP = 32 µs typical. TOSC = 50 ns minimum. TSCS = 8 TINP OR 8 TT1P. TDLY = 1 TINP OR 1 TT1P. DS30487C-page 46 2005 Microchip Technology Inc.
PIC16F87/88 4.7.3.2 Returning to Primary Oscillator with a Reset A Reset will clear SCS<1:0> back to ‘00’. The sequence for starting the primary oscillator following a Reset is the same for all forms of Reset, including POR. There is no transition sequence from the alternate system clock to the primary system clock on a Reset condition. Instead, the device will reset the state of the OSCCON register and default to the primary system clock.
PIC16F87/88 FIGURE 4-11: PRIMARY SYSTEM CLOCK AFTER RESET (EC, RC, INTRC) TT1P(1) Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0002h 0003h T1OSI OSC1 OSC2 TCPU(2) CPU Start-up System Clock MCLR OSTS Program Counter PC 0000h 0001h 0004h Note 1: TT1P = 30.52 µs. 2: TCPU = 5-10 µs (1 MHz system clock). DS30487C-page 48 2005 Microchip Technology Inc.
PIC16F87/88 TABLE 4-4: Current System Clock CLOCK SWITCHING MODES SCS Bits <1:0> Modified to: Delay OSTS Bit IOFS T1RUN Bit Bit New System Clock LP, XT, HS, 10 T1OSC, (INTRC) EC, RC FOSC<2:0> = LP, XT or HS 8 Clocks of INTRC 0 1(1) 0 LP, XT, HS, 01 INTRC, (T1OSC) EC, RC FOSC<2:0> = LP, XT or HS 8 Clocks of T1OSC 0 N/A 1 T1OSC EC or RC Comments INTRC The internal RC oscillator or frequency is dependant upon INTOSC the IRCF bits. or INTOSC Postscaler T1OSCEN bit must be enabled.
PIC16F87/88 4.7.4 EXITING SLEEP WITH AN INTERRUPT Any interrupt, such as WDT or INT0, will cause the part to leave the Sleep mode. The SCS bits are unaffected by a SLEEP command and are the same before and after entering and leaving Sleep. The clock source used after an exit from Sleep is determined by the SCS bits. 4.7.4.1 Sequence of Events If SCS<1:0> = 00: 1. 2. 3. The device is held in Sleep until the CPU start-up time-out is complete.
PIC16F87/88 5.0 I/O PORTS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023). 5.1 PORTA and the TRISA Register PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA.
PIC16F87/88 TABLE 5-2: Address SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000(1) xxx0 0000(2) uuuu 0000(1) uuu0 0000(2) 05h PORTA 85h TRISA 1111 1111 1111 1111 9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 — — — — 0000 ---- 0000 ---- 9Bh ANSEL(4) — ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 -111 1111 -111 1111 Legend: Note 1: 2: 3: 4: TRISA7
PIC16F87/88 FIGURE 5-2: Data Bus BLOCK DIAGRAM OF RA3/AN3/VREF+/C1OUT PIN Comparator Mode = 110 D Q Comparator 1 Output WR PORTA CK VDD VDD Q P Data Latch D Q RA3 pin N WR TRISA CK Q TRIS Latch VSS VSS Analog Input Mode TTL Input Buffer RD TRISA Q D EN RD PORTA To Comparator To A/D Module Channel Input (PIC16F88 only) To A/D Module Channel VREF+ Input (PIC16F88 only) FIGURE 5-3: Data Bus BLOCK DIAGRAM OF RA2/AN2/CVREF/VREF- PIN D Q VDD WR PORTA CK VDD Q P Data Latch D WR TRIS
PIC16F87/88 FIGURE 5-4: Data Bus BLOCK DIAGRAM OF RA4/AN4/T0CKI/C2OUT PIN Comparator Mode = 011, 101, 110 D Q Comparator 2 Output WR PORTA VDD 1 CK Q Data Latch D VDD P 0 Q RA4 pin N WR TRISA CK Q VSS Analog Input Mode TRIS Latch Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA TMR0 Clock Input To A/D Module Channel Input (PIC16F88 only) FIGURE 5-5: BLOCK DIAGRAM OF RA5/MCLR/VPP PIN MCLRE MCLR Circuit Schmitt Trigger Buffer MCLR Filter Data Bus RA5/MCLR/VPP pin Schmitt Trig
PIC16F87/88 FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN From OSC1 CLKO (FOSC/4) Oscillator Circuit VDD VDD P RA6/OSC2/CLKO pin Data Bus WR PORTA D Q CK VSS N (FOSC = 1x1) VSS VDD Q P Data Latch D WR TRISA Q N CK Q (FOSC = 1x0, 011) TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA (FOSC = 1x0, 011) Note 1: I/O pins have protection diodes to VDD and VSS. 2: CLKO signal is 1/4 of the FOSC frequency. 2005 Microchip Technology Inc.
PIC16F87/88 FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN From OSC2 Oscillator Circuit VDD (FOSC = 011) Data Bus D WR PORTA CK Q VDD Q P RA7/OSC1/CLKI pin(1) VSS Data Latch D WR TRISA Q N CK Q FOSC = 10x TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D EN FOSC = 10x RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS. DS30487C-page 56 2005 Microchip Technology Inc.
PIC16F87/88 5.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up.
PIC16F87/88 TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT/CCP1(7) bit 0 TTL/ST(1) Input/output pin or external interrupt input. Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up. RB1/SDI/SDA bit 1 TTL/ST(5) Input/output pin, SPI™ data input pin or I2C™ data I/O pin. Internal software programmable weak pull-up. RB2/SDO/RX/DT bit 2 TTL/ST(4) Input/output pin, SPI data output pin. AUSART asynchronous receive or synchronous data.
PIC16F87/88 FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT/CCP1(3) PIN CCP1M<3:0> = 1000, 1001, 11xx and CCPMX = 1 CCP 0 1 CCP1M<3:0> = 000 VDD RBPU(2) Data Bus WR PORTB Weak P Pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK RD TRISB Q RD PORTB D EN To INT0 or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F87/88 FIGURE 5-9: BLOCK DIAGRAM OF RB1/SDI/SDA PIN I2C™ Mode Port/SSPEN Select SDA Output 1 0 VDD RBPU(2) Data Bus WR PORTB Weak P Pull-up VDD Data Latch D Q P CK N I/O pin(1) VSS TRIS Latch D Q WR TRISB CK Q RD TRISB TTL Input Buffer SDA Drive Q D RD PORTB EN SDA(3) Schmitt Trigger Buffer RD PORTB SDI Note 1: 2: 3: DS30487C-page 60 I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F87/88 FIGURE 5-10: BLOCK DIAGRAM OF RB2/SDO/RX/DT PIN SSPEN SDO 1 0 SSPEN + SPEN SPEN DT 1 0 VDD RBPU(2) Weak P Pull-up VDD Data Latch Data Bus WR PORTB D P Q CK N I/O pin(1) VSS TRIS Latch D Q WR TRISB CK Q RD TRISB TTL Input Buffer DT Drive Q D RD PORTB EN Schmitt Trigger Buffer RD PORTB RX/DT Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2005 Microchip Technology Inc.
PIC16F87/88 BLOCK DIAGRAM OF RB3/PGM/CCP1(3) PIN FIGURE 5-11: CCP1M<3:0> = 1000, 1001, 11xx and CCPMX = 0 CCP1M<3:0> = 0100, 0101, 0110, 0111 and CCPMX = 0 CCP 0 or LVP = 1 1 VDD RBPU(2) Data Bus WR PORTB Weak P Pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK RD TRISB Q D RD PORTB EN To PGM or CCP RD PORTB Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F87/88 FIGURE 5-12: BLOCK DIAGRAM OF RB4/SCK/SCL PIN Port/SSPEN SCK/SCL 1 0 VDD RBPU(2) Weak P Pull-up VDD SCL Drive Data Bus WR PORTB P Data Latch D Q I/O pin(1) N CK TRIS Latch D WR TRISB VSS Q CK TTL Input Buffer RD TRISB Latch Q D EN RD PORTB Q1 Set RBIF Q From other RB7:RB4 pins D RD PORTB EN Q3 SCK SCL(3) Note 1: 2: 3: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F87/88 FIGURE 5-13: BLOCK DIAGRAM OF RB5/SS/TX/CK PIN RBPU(2) VDD Port/SSPEN Weak P Pull-up Data Latch Data Bus WR PORTB D Q I/O pin(1) CK TRIS Latch D WR TRISB Q CK TTL Input Buffer RD TRISB Latch Q D EN RD PORTB Q1 Set RBIF From other RB7:RB4 pins Q D RD PORTB EN Q3 Peripheral Input Note 1: 2: DS30487C-page 64 I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2005 Microchip Technology Inc.
PIC16F87/88 FIGURE 5-14: BLOCK DIAGRAM OF RB6/AN5(3)/PGC/T1OSO/T1CKI PIN Analog Input Mode VDD RBPU(2) Weak P Pull-up Data Latch Data Bus WR PORTB D Q I/O pin(1) CK TRIS Latch D WR TRISB Q CK Analog Input Mode RD TRISB TTL Input Buffer T1OSCEN/ICD/PROG Mode Latch Q D EN RD PORTB Q1 Set RBIF From other RB7:RB4 pins Q D RD PORTB EN Q3 PGC/T1CKI From T1OSCO Output To A/D Module Channel Input (PIC16F88 only) Note 1: 2: 3: I/O pins have diode protection to VDD and VSS.
PIC16F87/88 FIGURE 5-15: BLOCK DIAGRAM OF RB7/AN6(3)/PGD/T1OSI PIN Port/Program Mode/ICD PGD 1 0 Analog Input Mode VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D WR PORTB Q I/O pin(1) CK TRIS Latch D WR TRISB Q 0 CK RD TRISB T1OSCEN 1 T1OSCEN Analog Input Mode PGD DRVEN TTL Input Buffer Latch Q EN RD PORTB Set RBIF From other RB7:RB4 pins D Q Q1 D RD PORTB EN Q3 PGD To T1OSCI Input To A/D Module Channel Input (PIC16F88 only) Note 1: 2: 3: DS30487C-page 66 I/O pins have diod
PIC16F87/88 6.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/ T0CKI/C2OUT. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.3 “Using Timer0 with an External Clock”.
PIC16F87/88 6.3 Using Timer0 with an External Clock Note: When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns).
PIC16F87/88 EXAMPLE 6-1: CLRWDT BANKSEL MOVLW MOVWF 01h,101h ; ; ; ; OPTION_REG b'xxxx0xxx' OPTION_REG TABLE 6-1: Address CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0 Clear WDT and prescaler Select Bank of OPTION_REG Select TMR0, new prescale value and clock source REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 0Bh,8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 Module Register GIE PEIE TMR0IE INT0IE RBPU INTEDG T0CS T0SE Value on all other Resets x
PIC16F87/88 NOTES: DS30487C-page 70 2005 Microchip Technology Inc.
PIC16F87/88 7.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>).
PIC16F87/88 REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 R-0 R/W-0 R/W-0 — T1RUN T1CKPS1 T1CKPS0 R/W-0 R/W-0 R/W-0 R/W-0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00
PIC16F87/88 7.2 Timer1 Operation in Timer Mode 7.4 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync. 7.3 Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RB7/PGD/T1OSI when bit T1OSCEN is set, or on pin RB6/PGC/T1OSO/T1CKI when bit T1OSCEN is cleared.
PIC16F87/88 7.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt-on-overflow that will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 7.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”).
PIC16F87/88 7.6 TABLE 7-1: Timer1 Oscillator A crystal oscillator circuit is built between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator, rated up to 32.768 kHz. It will continue to run during all power-managed modes. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 7-3. Table 7-1 shows the capacitor selection for the Timer1 oscillator.
PIC16F87/88 7.8 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” signal (CCP1M3:CCP1M0 = 1011), the signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit, TMR1IF (PIR1<0>). Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
PIC16F87/88 EXAMPLE 7-3: RTCinit BANKSEL MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BANKSEL BSF RETURN BANKSEL BSF BCF INCF MOVF SUBLW BTFSS RETURN CLRF INCF MOVF SUBLW BTFSS RETURN CLRF INCF MOVF SUBLW BTFSS RETURN CLRF RETURN RTCisr TABLE 7-2: Address IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE TMR1H TMR1H, 7 PIR1, TMR1IF secs, F secs, w .60 STATUS, Z seconds mins, f mins, w .60 STATUS, Z mins hours, f hours, w .
PIC16F87/88 NOTES: DS30487C-page 78 2005 Microchip Technology Inc.
PIC16F87/88 8.0 TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP1 module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2.
PIC16F87/88 REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — R/W-0 R/W-0 TOUTPS3 TOUTPS2 R/W-0 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = P
PIC16F87/88 9.0 CAPTURE/COMPARE/PWM (CCP) MODULE The CCP module’s input/output pin (CCP1) can be configured as RB0 or RB3. This selection is set in bit 12 (CCPMX) of the Configuration Word. The Capture/Compare/PWM (CCP) module contains a 16-bit register that can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register. Table 9-1 shows the timer resources of the CCP module modes.
PIC16F87/88 9.1 9.1.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on the CCP1 pin. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 9.1.1 CCP PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the TRISB bit. Note 1: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition.
PIC16F87/88 9.2 9.2.1 Compare Mode CCP PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the TRISB bit. In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 pin is: Note 1: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the data latch.
PIC16F87/88 9.3 9.3.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTB I/O data latch. Figure 9-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F87/88 9.3.3 The maximum PWM resolution (bits) for a given PWM frequency is given by the following formula. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 9-3: Resolution FOSC log FPWM ( = log(2) 1. ) 2. bits 3. Note: SETUP FOR PWM OPERATION If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. 4. 5. Set the PWM period by writing to the PR2 register.
PIC16F87/88 NOTES: DS30487C-page 86 2005 Microchip Technology Inc.
PIC16F87/88 10.0 10.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F87/88 REGISTER 10-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 SMP R/W-0 CKE R-0 R-0 R-0 R-0 R-0 R-0 D/A (1) (1) R/W UA BF P S bit 7 bit 0 bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: This bit must be cleared when SPI is used in Slave mode. I2C mode: This bit must be maintained clear.
PIC16F87/88 REGISTER 10-2: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 WCOL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = An attempt to write the SSPBUF register failed because the SSP module is busy (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holdin
PIC16F87/88 FIGURE 10-1: SSP BLOCK DIAGRAM (SPI™ MODE) To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear bit SSPEN, reinitialize the SSPCON register and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISB register) appropriately programmed.
PIC16F87/88 FIGURE 10-2: SPI™ MODE TIMING (MASTER MODE) SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit 7 SDO bit 6 bit 5 bit 2 bit 3 bit 4 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SDI (SMP = 1) bit 7 bit 0 SSPIF FIGURE 10-3: SPI™ MODE TIMING (SLAVE MODE WITH CKE = 0) SS (Optional) SCK (CKP = 0) SCK (CKP = 1) bit 7 SDO bit 6 bit 5 bit 2 bit 3 bit 4 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SSPIF FIGURE 10-4: SPI™ MODE TIMING (SLAVE MO
PIC16F87/88 10.3 SSP I 2C Mode Operation The SSP module in I2C mode fully implements all slave functions, except general call support and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RB4/ SCK/SCL pin, which is the clock (SCL) and the RB1/ SDI/SDA pin, which is the data (SDA).
PIC16F87/88 10.3.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISB<4,1> set). The SSP module will override the input state with the output data when required (slave-transmitter). The sequence of events for 10-bit Address mode is as follows, with steps 7-9 for slave transmitter: 1. 2.
PIC16F87/88 An SSP interrupt is generated for each data transfer byte. Flag bit, SSPIF, must be cleared in software and the SSPSTAT register is used to determine the status of the byte. Flag bit, SSPIF, is set on the falling edge of the ninth clock pulse. the data transfer is complete. When the ACK is latched by the slave device, the slave logic is reset (resets SSPSTAT register) and the slave device then monitors for another occurrence of the Start bit.
PIC16F87/88 10.3.2 MASTER MODE OPERATION 10.3.3 Master mode operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset, or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle and both the S and P bits are clear.
PIC16F87/88 NOTES: DS30487C-page 96 2005 Microchip Technology Inc.
PIC16F87/88 11.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The AUSART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is one of the two serial I/O modules. (AUSART is also known as a Serial Communications Interface or SCI.
PIC16F87/88 REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RB2/SDO/RX/DT and RB5/SS/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t ca
PIC16F87/88 11.1 11.1.1 AUSART Baud Rate Generator (BRG) The PIC16F87/88 has an 8 MHz INTRC that can be used as the system clock, thereby eliminating the need for external components to provide the clock source. When the INTRC provides the system clock, the AUSART module will also use the INTRC as its system clock. Table 11-1 shows some of the INTRC frequencies that can be used to generate the AUSART module’s baud rate. The BRG supports both the Asynchronous and Synchronous modes of the AUSART.
PIC16F87/88 TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz BAUD RATE (K) % ERROR KBAUD FOSC = 16 MHz SPBRG value (decimal) % ERROR KBAUD FOSC = 10 MHz SPBRG value (decimal) KBAUD % ERROR SPBRG value (decimal) 0.3 — — — — — — — — — 1.2 1.221 +1.75 255 1.202 +0.17 207 1.202 +0.17 129 2.4 2.404 +0.17 129 2.404 +0.17 103 2.404 +0.17 64 9.6 9.766 +1.73 31 9.615 +0.16 25 9.766 +1.73 15 19.2 19.531 + 1.72 15 19.231 +0.16 12 19.
PIC16F87/88 TABLE 11-5: INTRC BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 8 MHz BAUD RATE (K) KBAUD % ERROR FOSC = 4 MHz SPBRG value (decimal) KBAUD FOSC = 2 MHz % ERROR SPBRG value (decimal) KBAUD FOSC = 1 MHz % ERROR SPBRG value (decimal) KBAUD % ERROR SPBRG value (decimal) 0.3 NA — — 0.300 0 207 0.300 0 103 0.300 0 51 1.2 1.202 +0.16 103 1.202 +0.16 51 1.202 +0.16 25 1.202 +0.16 12 2.4 2.404 +0.16 51 2.404 +0.16 25 2.404 +0.16 12 2.232 -6.
PIC16F87/88 11.2 AUSART Asynchronous Mode interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty.
PIC16F87/88 When setting up an asynchronous transmission, follow these steps: 4. 1. 5. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 11.1 “AUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. 2. 3. FIGURE 11-2: If 9-bit transmission is desired, then set transmit bit TX9.
PIC16F87/88 11.2.2 AUSART ASYNCHRONOUS RECEIVER is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full, the Overrun Error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software.
PIC16F87/88 When setting up an asynchronous reception, follow these steps: 1. 2. 3. 4. 5. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10.
PIC16F87/88 11.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT • Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. • Read the 8-bit received data by reading the RCREG register to determine if the device is being addressed. • If any error occurred, clear the error by clearing enable bit CREN.
PIC16F87/88 FIGURE 11-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT RB2/SDO/RX/DT pin Start bit bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit Load RSR Bit 8 = 0, Data Byte Bit 8 = 1, Address Byte Word 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN = 1.
PIC16F87/88 11.3 AUSART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RB5/SS/TX/CK and RB2/SDO/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16F87/88 TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Address Name 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch PIR1 18h RCSTA 19h TXREG Bit 6 GIE PEIE — ADIF(1) RCIF SPEN RX9 SREN PIE1 98h TXSTA 99h SPBRG Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 CCP1IE TMR
PIC16F87/88 11.3.2 AUSART SYNCHRONOUS MASTER RECEPTION receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register, before reading RCREG, in order not to lose the old RX9D information. Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RB2/SDO/RX/DT pin on the falling edge of the clock.
PIC16F87/88 FIGURE 11-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RB2/SDO/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RB5/SS/TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. 11.
PIC16F87/88 11.4.2 AUSART SYNCHRONOUS SLAVE RECEPTION When setting up a synchronous slave reception, follow these steps: The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode. Bit SREN is a “don’t care” in Slave mode. 1. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep.
PIC16F87/88 12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has five registers: The Analog-to-Digital (A/D) converter module has seven inputs for 18/20 pin devices (PIC16F88 devices only). The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has a high and low-voltage reference input that is software selectable to some combination of VDD, VSS, VREF- (RA2) or VREF+ (RA3).
PIC16F87/88 REGISTER 12-2: ADCON0: A/D CONTROL REGISTER (ADDRESS 1Fh) PIC16F88 DEVICES ONLY R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits If ADCS2 = 0: 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) If ADCS2 = 1: 00 = FOSC/4 01 = FOSC/16 10 = FOSC/64 11 = FRC (clock derived from the internal A/D module RC oscillator) bit 5-3
PIC16F87/88 REGISTER 12-3: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) PIC16F88 DEVICES ONLY R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 ADFM ADCS2 VCFG1 VCFG0 — — — — bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
PIC16F87/88 The ADRESH:ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the A/D Result register pair, the GO/DONE bit (ADCON0<2>) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 12-1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC16F87/88 12.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-2.
PIC16F87/88 12.2 Selecting the A/D Conversion Clock 12.3 Operation in Power-Managed Modes The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. The seven possible options for TAD are: The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode.
PIC16F87/88 12.4 Configuring Analog Port Pins 12.5 The ADCON1, ANSEL, TRISA and TRISB registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. Clearing the GO/DONE bit during a conversion will abort the current conversion.
PIC16F87/88 12.6 A/D Operation During Sleep 12.7 The A/D module can operate during Sleep mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRES registers.
PIC16F87/88 13.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins RA0 through RA3, while the outputs are multiplexed to pins RA3 and RA4. The on-chip Voltage Reference (Section 14.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 13-1: The CMCON register (Register 13-1) controls the comparator input and output multiplexors.
PIC16F87/88 13.1 Comparator Configuration Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 13-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode.
PIC16F87/88 13.2 13.3.2 Comparator Operation A single comparator is shown in Figure 13-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC16F87/88 FIGURE 13-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX CnINV To Data Bus Q D Q1 EN RD_CMCON Q Set CMIF bit D Q3 * RD_CMCON EN CL From other Comparator 13.6 RESET Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC16F87/88 13.7 Comparator Operation During Sleep 13.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications.
PIC16F87/88 TABLE 13-1: Address REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111 9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 0Bh, 8Bh, INTCON 10Bh, 18Bh GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u — EEIF — — — — 00-0 ---- 00-0 ---00-0 ---- 00-0 ---- 0
PIC16F87/88 14.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode ‘010’. A programmable register controls the function of the reference generator. Register 14-1 lists the bit functions of the CVRCON register.
PIC16F87/88 FIGURE 14-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VDD 16 Stages CVREN 8R R R R R 8R CVRR RA2/AN2/CVREF/VREF- pin(1) CVROE CVREF Input to Comparator CVR3 CVR2 CVR1 CVR0 16-to-1 Analog MUX Note 1: VREF is available on the PIC16F88 device only.
PIC16F87/88 15.
PIC16F87/88 REGISTER 15-1: R/P-1 CP R/P-1 CONFIG1: CONFIGURATION WORD 1 REGISTER (ADDRESS 2007h) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CCPMX DEBUG WRT1 WRT0 CPD LVP R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit 0 bit 13 CP: Flash Program Memory Code Protection bits 1 = Code protection off 0 = 0000h to 0FFFh code-protected (all protected) bit 12 CCPMX: CCP1 Pin Selection bit 1 = CCP1 function on RB0 0 = CCP1 function on RB3 bit 11 DEBUG: In-C
PIC16F87/88 REGISTER 15-2: CONFIG2: CONFIGURATION WORD 2 REGISTER (ADDRESS 2008h) U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — — — — — — — IESO FCMEN bit 13 bit 0 bit 13-2 Unimplemented: Read as ‘1’ bit 1 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 0 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor d
PIC16F87/88 15.2 Reset The PIC16F87/88 differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset during normal operation WDT wake-up during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset.
PIC16F87/88 15.3 MCLR PIC16F87/88 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR and excessive current beyond the device specification during the ESD event.
PIC16F87/88 15.8 Time-out Sequence 15.9 On power-up, the time-out sequence is as follows: the PWRT delay starts (if enabled) when a POR occurs. Then, OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of Reset. The Power Control/Status Register, PCON, has two bits to indicate the type of Reset that last occurred. Bit 0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset.
PIC16F87/88 TABLE 15-3: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu PC + 1 uuu0 0uuu ---- --uu 000h 0001 1uuu ---- --u0 uuu1 0uuu ---- --uu Condition WDT Wake-up Brown-out Reset (1) Interrupt Wake-up from Sleep PC + 1 Legend: u = unchanged, x = unknown, -
PIC16F87/88 TABLE 15-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset Wake-up via WDT or Interrupt TXREG 0000 0000 0000 0000 uuuu uuuu RCREG 0000 0000 0000 0000 uuuu uuuu ADRESH xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 1111 1111 1111 1111 uuuu uuuu TRISA 1111 1111 1111 1111 uuuu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu PIE1 -000 0000 -000 0000 -uuu uuuu PIE2 00
PIC16F87/88 FIGURE 15-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR) VDD MCLR INTERNAL POR TPWRT TOST PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 15-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 15-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INT
PIC16F87/88 FIGURE 15-6: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 15.10 Interrupts The PIC16F87/88 has up to 12 sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit.
PIC16F87/88 FIGURE 15-7: INTERRUPT LOGIC EEIF EEIE OSFIF OSFIE ADIF ADIE TMR0IF TMR0IE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE INT0IF INT0IE Wake-up (if in Sleep mode) Interrupt to CPU RBIF RBIE PEIE GIE TMR2IF TMR2IE TMR1IF TMR1IE CMIF CMIE 2005 Microchip Technology Inc.
PIC16F87/88 15.10.1 INT INTERRUPT 15.10.3 External interrupt on the RB0/INT pin is edge-triggered, either rising if bit INTEDG (OPTION_REG<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit, INT0IF (INTCON<1>), is set. This interrupt can be disabled by clearing enable bit INT0IE (INTCON<4>). Flag bit INT0IF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F87/88 15.12 Watchdog Timer (WDT) A new prescaler has been added to the path between the internal RC and the multiplexors used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the internal RC by 32 to 65536, giving the time base used for the WDT a nominal range of 1 ms to 2.097s. For PIC16F87/88 devices, the WDT has been modified from previous PIC16 devices.
PIC16F87/88 REGISTER 15-3: WDTCON: WATCHDOG CONTROL REGISTER (ADDRESS 105h) U-0 U-0 U-0 R/W-0 — — — WDTPS3 R/W-1 R/W-0 R/W-0 R/W-0 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Prescale Value Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16394 1010 = 1:32768 1011 = 1:65536 bit 0 SWDTEN: Software Enable/Disable fo
PIC16F87/88 15.12.3 TWO-SPEED CLOCK START-UP MODE Two-Speed Start-up mode minimizes the latency between oscillator start-up and code execution that may be selected with the IESO (Internal/External Switchover) bit in Configuration Word 2. This mode is achieved by initially using the INTRC for code execution until the primary oscillator is stable. If this mode is enabled and any of the following conditions exist, the system will begin execution with the INTRC oscillator.
PIC16F87/88 15.12.4 FAIL-SAFE OPTION The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate even in the event of an oscillator failure. FIGURE 15-10: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock S INTRC Oscillator ÷ 64 31.25 kHz (32 µs) 488 Hz (2.048 ms) C Q Q Clock Failure Detected The FSCM function is enabled by setting the FCMEN bit in Configuration Word 2.
PIC16F87/88 15.12.4.2 FSCM and the Watchdog Timer 2. After a POR (Power-on Reset), the device is running in Two-Speed Start-up mode. The crystal fails before the OST has expired. If a crystal fails during the OST period, a fail-safe condition will not be detected (OSFIF will not get set). OSTS = 0 SCS = 00 OSFIF = 0 When a clock failure is detected, SCS<1:0> will be forced to ‘10’ which will reset the WDT (if enabled). 15.12.4.
PIC16F87/88 15.13.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a peripheral interrupt. External MCLR Reset will cause a device Reset. All other events are considered a continuation of program execution and cause a “wake-up”. The TO and PD bits in the STATUS register can be used to determine the cause of the device Reset.
PIC16F87/88 15.14 In-Circuit Debugger When the DEBUG bit in the Configuration Word is programmed to a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB® ICD. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 15-7 shows which features are consumed by the background debugger.
PIC16F87/88 15.18 Low-Voltage ICSP Programming The LVP bit of the Configuration Word enables LowVoltage ICSP Programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin.
PIC16F87/88 16.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16F87/88 TABLE 16-2: PIC16F87/88 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Mov
PIC16F87/88 16.2 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + k → (W) Status Affected: C, DC, Z Operation: (W) .AND. (f) → (destination) The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: Z Description: AND the W register with register ‘f’.
PIC16F87/88 BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ f ≤ 127 Operation: Operation: skip if (f) = 1 00h → (f), 1→Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ = 0, the next instruction is executed. If bit ‘b’ = 1, then the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction.
PIC16F87/88 COMF Complement f Syntax: [ label ] COMF GOTO Unconditional Branch Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 2047 Operation: (f) → (destination) Operation: k → PC<10:0>, PCLATH<4:3> → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are complemented. If ‘d’ = 0, the result is stored in W. If ‘d’ = 1, the result is stored back in register ‘f’. Description: GOTO is an unconditional branch.
PIC16F87/88 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Description: The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Description: The eight-bit literal ‘k’ is loaded into W register. The don’t cares will assemble as ‘0’s.
PIC16F87/88 RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS → PC, 1 → GIE 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ = 0, the result is placed in the W register. If ‘d’ = 1, the result is stored back in register ‘f’.
PIC16F87/88 SUBLW Syntax: Subtract W from Literal [ label ] SUBLW k XORLW Exclusive OR Literal with W Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: k – (W) → (W) XORLW k Operation: (W) .XOR. k → (W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (two’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F87/88 17.
PIC16F87/88 17.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 17.
PIC16F87/88 17.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F87/88 17.14 PICSTART Plus Development Programmer 17.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins.
PIC16F87/88 17.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development.
PIC16F87/88 NOTES: DS30487C-page 162 2005 Microchip Technology Inc.
PIC16F87/88 18.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.
PIC16F87/88 FIGURE 18-1: PIC16F87/88 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 16 MHz 20 MHz Frequency FIGURE 18-2: PIC16LF87/88 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (12 MHz/V) (VDDAPPMIN – 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16F87/88 18.1 DC Characteristics: Supply Voltage PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions 0.1 0.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.2 DC Characteristics: Power-Down and Supply Current PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F87/88 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87/88 18.3 DC Characteristics: Internal RC Accuracy PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) PIC16LF87/88 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended PIC16F87/88 (Industrial, Extended) Param No.
PIC16F87/88 18.4 DC Characteristics: PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) DC CHARACTERISTICS Param Sym No. VIL Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 18.1 “DC Characteristics: Supply Voltage”. Characteristic Min Typ† Max Units Conditions VSS — 0.15 VDD V For entire VDD range VSS — 0.8V V 4.
PIC16F87/88 18.4 DC Characteristics: PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued) DC CHARACTERISTICS Param Sym No. VOL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 18.1 “DC Characteristics: Supply Voltage”. Min Typ† Max Units Conditions Output Low Voltage D080 I/O ports — — 0.
PIC16F87/88 TABLE 18-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.
PIC16F87/88 18.5 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F87/88 FIGURE 18-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 18-3: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC Characteristic External CLKI Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKI Period (Note 1) Oscillator Period (Note 1) Min Typ† Max Units Conditions DC — 1 MHz XT and RC Oscillator mode DC — 20 MHz HS Oscillator mode DC — 32 kHz DC — 4 MHz RC Oscillator mode 0.
PIC16F87/88 FIGURE 18-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 18-3 for load conditions. TABLE 18-4: Param No.
PIC16F87/88 FIGURE 18-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 18-3 for load conditions. FIGURE 18-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 18-5: Parameter No.
PIC16F87/88 FIGURE 18-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RB6/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 18-3 for load conditions. TABLE 18-6: Param No. 40* TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Symbol Tt0H Characteristic T0CKI High Pulse Width Min Typ† Max Units No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 0.
PIC16F87/88 FIGURE 18-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1) CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 18-3 for load conditions. TABLE 18-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Symbol No. 50* TccL Characteristic Min CCP1 No Prescaler Input Low Time With Prescaler PIC16F87/88 PIC16LF87/88 51* TccH CCP1 No Prescaler Input High Time With Prescaler PIC16F87/88 PIC16LF87/88 0.5 TCY + 20 Typ† Max Units — — ns 10 — — ns 20 — — ns 0.
PIC16F87/88 FIGURE 18-10: SPI™ MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI Bit 6 - - - -1 MSb In LSb In 74 73 Note: Refer to Figure 18-3 for load conditions. FIGURE 18-11: SPI™ MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb LSb Bit 6 - - - - - -1 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 Note: Refer to Figure 18-3 for load conditions.
PIC16F87/88 FIGURE 18-12: SPI™ SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 LSb Bit 6 - - - - - -1 MSb SDO 77 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 18-3 for load conditions. FIGURE 18-13: SPI™ SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO Bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 Bit 6 - - - -1 LSb In 74 Note: Refer to Figure 18-3 for load conditions.
PIC16F87/88 TABLE 18-8: Param No.
PIC16F87/88 TABLE 18-9: Param No.
PIC16F87/88 TABLE 18-10: I2C™ BUS DATA REQUIREMENTS Param. No. 100* Symbol THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode SSP Module 101* TLOW Clock Low Time TR 103* TF 90* TSU:STA 91* THD:STA THD:DAT 106* 107* TSU:DAT TSU:STO 92* 109* TAA 110* TBUF CB * Note 1: 2: Max Units 4.0 — µs 0.6 — µs 1.5 TCY — 100 kHz mode 4.7 — µs 400 kHz mode 1.3 — µs SSP Module 102* Min SDA and SCL Rise 100 kHz mode Time 400 kHz mode 1.5 TCY — — 1000 ns 20 + 0.
PIC16F87/88 FIGURE 18-16: AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RB5/SS/TX/CK pin 121 121 RB2/SDO/RX/DT pin 120 122 Note: Refer to Figure 18-3 for load conditions. TABLE 18-11: AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16F87/88 TABLE 18-13: A/D CONVERTER CHARACTERISTICS: PIC16F87/88 (INDUSTRIAL, EXTENDED) PIC16LF87/88 (INDUSTRIAL) Param Sym No. Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10-bit bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A06 EOFF Offset Error — — <±2 LSb VREF = VDD = 5.
PIC16F87/88 FIGURE 18-18: A/D CONVERSION TIMING 1 TCY BSF ADCON0, GO (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 ... 7 ... 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE Sampling Stopped SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 18-14: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period — — µs TOSC based, VREF ≥ 3.
PIC16F87/88 NOTES: DS30487C-page 192 2005 Microchip Technology Inc.
PIC16F87/88 19.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F87/88 FIGURE 19-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.6 5.5V 1.4 5.0V 1.2 4.5V IDD (mA) 4.0V 1.0 3.5V 0.8 3.0V 2.5V 0.6 2.0V 0.4 0.2 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 3500 4000 FOSC (MHz) FIGURE 19-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.
PIC16F87/88 FIGURE 19-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 70 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 60 5.5V 5.0V 50 4.5V IDD (uA) 40 4.0V 3.5V 30 3.0V 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 19-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 100 5.5V 5.0V 4.5V 80 IDD (uA) 4.
PIC16F87/88 FIGURE 19-7: TYPICAL IDD vs. VDD, -40°C TO +125°C, 1 MHz TO 8 MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.4 5.5V 5.0V 1.2 4.5V 1.0 IDD (mA) 4.0V 3.5V 0.8 3.0V 0.6 2.5V 0.4 2.0V 0.2 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 FOSC (MHz) FIGURE 19-8: MAXIMUM IDD vs. VDD, -40°C TO +125°C, 1 MHz TO 8 MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 4.
PIC16F87/88 FIGURE 19-9: IDD vs. VDD, SEC_RUN MODE, -10°C TO +125°C, 32.768 kHz (XTAL 2 x 22 pF, ALL PERIPHERALS DISABLED) 45.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 40.0 35.0 Max (+70°C) Idd(µA) 30.0 25.0 Typ (+25°C) 20.0 15.0 10.0 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vdd(V) FIGURE 19-10: IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (125°C) 10 Max (85°C) IPD (uA) 1 0.1 0.
PIC16F87/88 FIGURE 19-11: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25°C) 4.5 Operation above 4 MHz is not recommended 4.0 5.1 kOhm 3.5 Freq (MHz) 3.0 2.5 10 kOhm 2.0 1.5 1.0 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25°C) 2.5 2.0 3.3 kOhm Freq (MHz) 1.5 5.1 kOhm 1.0 10 kOhm 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F87/88 FIGURE 19-13: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25°C) 0.9 0.8 3.3 kOhm 0.7 0.6 Freq (MHz) 5.1 kOhm 0.5 0.4 10 kOhm 0.3 0.2 0.1 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-14: ∆IPD TIMER1 OSCILLATOR, -10°C TO +70°C (SLEEP MODE, TMR1 COUNTER DISABLED) IPD Timer1 Oscillator, -10°C to +70°C SLEEP mode, TMR1 counter disabled 5.0 4.5 Max (-10°C to +70°C) 4.0 3.5 3.0 IPD (µA) Typ (+25°C) 2.5 2.0 1.
PIC16F87/88 FIGURE 19-15: ∆IPD WDT, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 18 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 16 14 ∆IWDT (µA) 12 10 Max (-40°C to +125°C) 8 6 Max (-40°C to +85°C) 4 2 Typ (25°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-16: ∆IPD BOR vs. VDD, -40°C TO +125°C (SLEEP MODE, BOR ENABLED AT 2.00V-2.
PIC16F87/88 FIGURE 19-17: IPD A/D, -40°C TO +125°C, SLEEP MODE, A/D ENABLED (NOT CONVERTING) 12 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 10 Max (-40°C to +125°C) ∆IA/D (µA) 8 6 4 Max (-40°C to +85°C) 2 Typ (+25°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-18: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C) 5.5 5.0 4.5 4.0 Max 3.5 VOH (V) Typ (25°C) 3.0 2.5 Min 2.
PIC16F87/88 FIGURE 19-19: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C) 3.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.0 2.5 Max VOH (V) 2.0 Typ (25°C) 1.5 Min 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 19-20: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C) 1.0 0.
PIC16F87/88 FIGURE 19-21: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C) 3.0 Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 2.5 VOL (V) 2.0 1.5 Max (85°C) 1.0 Typ (25°C) 0.5 Min (-40°C) 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 19-22: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C) 1.5 1.
PIC16F87/88 FIGURE 19-23: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.5 VIH Max (125°C) 3.0 VIN (V) 2.5 VIH Min (-40°C) 2.0 VIL Max (-40°C) 1.5 1.0 VIL Min (125°C) 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 19-24: MINIMUM AND MAXIMUM VIN vs. VDD (I2C™ INPUT, -40°C TO +125°C) 3.
PIC16F87/88 FIGURE 19-25: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C) 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.5 1 0.5 +125°C 125C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) FIGURE 19-26: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.
PIC16F87/88 NOTES: DS30487C-page 206 2005 Microchip Technology Inc.
PIC16F87/88 20.0 PACKAGING INFORMATION 20.1 Package Marking Information 18-Lead PDIP Example PIC16F88-I/P e3 0510017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC16F88 -I/SO e3 0510017 YYWWNNN 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC16F87/88 18-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
PIC16F87/88 18-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) E p E1 D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .
PIC16F87/88 20-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP) E E1 p D B 2 1 n c A2 A f L Units Dimension Limits n p MIN A1 INCHES NOM 20 .026 .069 .307 .209 .283 .030 4° - MAX MILLIMETERS* NOM 20 0.65 1.65 1.75 0.05 7.40 7.80 5.00 5.30 .295 7.20 0.55 0.75 0.09 0° 4° 0.22 - MIN Number of Pins Pitch Overall Height A .079 Molded Package Thickness A2 .065 .073 Standoff A1 .002 Overall Width E .291 .323 Molded Package Width E1 .197 .220 Overall Length D .272 .
PIC16F87/88 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN) EXPOSED METAL PAD E E1 Q D1 D D2 p 2 1 B n R E2 CH X 45° TOP VIEW L BOTTOM VIEW ı α A2 A A1 A3 Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Width Molded Package Width Exposed Pad Width Overall Length Molded Package Length Exposed Pad Length Lead Width Lead Length Tie Bar Width Tie Bar Length Chamfer Mold Draft Angle Top
PIC16F87/88 NOTES: DS30487C-page 212 2005 Microchip Technology Inc.
PIC16F87/88 APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (November 2003) DEVICE DIFFERENCES Original data sheet for PIC16F87/88 devices. The differences between the devices in this data sheet are listed in Table B-1. Revision B (August 2003) TABLE B-1: The specifications in Section 18.0 “Electrical Characteristics” have been updated to include the addition of maximum specifications to the DC Characteristics tables, text clarification has been made to Section 4.6.
PIC16F87/88 NOTES: DS30487C-page 214 2005 Microchip Technology Inc.
PIC16F87/88 INDEX A INTRC Baud Rates, Asynchronous Mode (BRGH = 0) .............................................. 101 INTRC Baud Rates, Asynchronous Mode (BRGH = 1) .............................................. 101 INTRC Operation ............................................... 99 Low-Power Mode Operation .............................. 99 Sampling ........................................................... 99 Clock Source Select (CSRC Bit) ...............................
PIC16F87/88 RB6/AN5/PGC/T1OSO/T1CKI Pin ............................. 65 RB7/AN6/PGD/T1OSI Pin .......................................... 66 Simplified PWM .......................................................... 84 SSP in I2C Mode ........................................................ 92 SSP in SPI Mode ....................................................... 90 System Clock ............................................................. 41 Timer0/WDT Prescaler ............................................
PIC16F87/88 Development Support ...................................................... 157 Device Differences ........................................................... 213 Device Overview .................................................................. 5 Direct Addressing ............................................................... 26 E EEADR Register .......................................................... 16, 27 EEADRH Register ........................................................
PIC16F87/88 Interrupts, Enable Bits A/D Converter Interrupt Enable (ADIE Bit) ................. 20 AUSART Receive Interrupt Enable (RCIE Bit) ........... 20 AUSART Transmit Interrupt Enable (TXIE Bit) .......... 20 CCP1 Interrupt Enable (CCP1IE Bit) ......................... 20 Comparator Interrupt Enable (CMIE Bit) .................... 22 EEPROM Write Operation Interrupt Enable (EEIE Bit) ............................................... 22 Global Interrupt Enable (GIE Bit) .......................
PIC16F87/88 PIR2 Register ..................................................................... 14 CMIF Bit ..................................................................... 23 EEIF Bit ...................................................................... 23 OSFIF Bit ................................................................... 23 POP ................................................................................... 25 POR. See Power-on Reset. PORTA .............................................
PIC16F87/88 S SCI. See AUSART. SCL .................................................................................... 93 Serial Communication Interface. See AUSART. Slave Mode SCL ............................................................................ 93 SDA ............................................................................ 93 Sleep ................................................................ 129, 132, 145 Software Simulator (MPLAB SIM) ....................................
PIC16F87/88 SPI Master Mode ....................................................... 91 SPI Master Mode (CKE = 0, SMP = 0) .................... 184 SPI Master Mode (CKE = 1, SMP = 1) .................... 184 SPI Slave Mode (CKE = 0) ................................ 91, 185 SPI Slave Mode (CKE = 1) ................................ 91, 185 Switching to SEC_RUN Mode ................................... 44 Synchronous Reception (Master Mode, SREN) .....................................
PIC16F87/88 NOTES: DS30487C-page 222 2005 Microchip Technology Inc.
PIC16F87/88 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F87/88 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F87/88 PIC16F87/88 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F87: Standard VDD range PIC16F87T: (Tape and Reel) PIC16LF87: Extended VDD range Temperature Range I E Package P SO SS ML = = = PIC16F87-I/P = Industrial temp., PDIP package, Extended VDD limits. PIC16F87-I/SO = Industrial temp.
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