Datasheet

 2001-2013 Microchip Technology Inc. DS39582C-page 93
PIC16F87XA
FIGURE 9-14: I
2
C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA SCL SSPIF BF (SSPSTAT<0>)
S
123456789 123456789 12345 789
P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>)
Cleared in software
Receive Second Byte of Address
Cleared by hardware when SSPADD is updated with low byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until update of SSPADD has taken place
UA is set indicating that SSPADD needs to be updated
UA is set indicating that SSPADD needs to be updated
Cleared by hardware when SSPADD is updated with high byte of address after falling edge
SSPBUF is written with contents of SSPSR
Dummy read of SSPBUF to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software
Cleared in software
SSPOV (SSPCON<6>)
CKP written to ‘1’
Note:An update of the SSPADD register
before the falling edge of the ninth clock will have no effect on UA, and UA will remain set.
Note:An update of the SSPADD register
before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
in software
Clock is held low until update of SSPADD has taken place
of ninth clock
of ninth clock
SSPOV is set because SSPBUF is still full. ACK is not sent.
Dummy read of SSPBUF to clear BF flag
Clock is held low until CKP is set to ‘1’
Clock is not held low because ACK = 1