Datasheet

 2001-2013 Microchip Technology Inc. DS39582C-page 89
PIC16F87XA
FIGURE 9-11: I
2
C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA SCL SSPIF BF (SSPSTAT<0>)
S
1234 56789 1 2345 6789 12345 789
P
1111 0A9A8 A7 A6A5A4A3A2A1A0 11110 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when SSPADD is updated with low byte of address
UA (SSPSTAT<1>)
Clock is held low until update of SSPADD has taken place
UA is set indicating that the SSPADD needs to be updated
UA is set indicating that SSPADD needs to be updated
Cleared by hardware when SSPADD is updated with high byte of address
SSPBUF is written with contents of SSPSR
Dummy read of SSPBUF to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Completion of clears BF flag
CKP (SSPCON<4>)
CKP is set in software
CKP is automatically cleared in hardware holding SCL low
Clock is held low until update of SSPADD has taken place
data transmission
Clock is held low until CKP is set to ‘1’
BF flag is clear third address sequence at the end of the