Datasheet

PIC16F87XA
DS39582C-page 48  2001-2013 Microchip Technology Inc.
4.4 PORTD and TRISD Registers
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configurable as an input
or output.
PORTD can be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit, PSPMODE (TRISE<4>). In this mode, the
input buffers are TTL.
FIGURE 4-8: PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-7: PORTD FUNCTIONS
TABLE 4-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Note: PORTD and TRISD are not implemented
on the 28-pin devices.
Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
TRIS
Name Bit# Buffer Type Function
RD0/PSP0 bit 0 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 0.
RD1/PSP1 bit 1 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 1.
RD2/PSP2 bit2 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 2.
RD3/PSP3 bit 3 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 3.
RD4/PSP4 bit 4 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 4.
RD5/PSP5 bit 5 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 5.
RD6/PSP6 bit 6 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 6.
RD7/PSP7 bit 7 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE
IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.