Datasheet

PIC16F87XA
DS39582C-page 192 2001-2013 Microchip Technology Inc.
TABLE 17-11: I
2
C BUS DATA REQUIREMENTS
Param
No.
Sym Characteristic Min Max Units Conditions
100 T
HIGH Clock High Time 100 kHz mode 4.0 s
400 kHz mode 0.6 s
SSP Module 0.5 T
CY
101 T
LOW Clock Low Time 100 kHz mode 4.7 s
400 kHz mode 1.3 s
SSP Module 0.5 T
CY
102 T
R SDA and SCL Rise
Time
100 kHz mode 1000 ns
400 kHz mode 20 + 0.1 C
B 300 ns Cb is specified to be from 10 to
400 pF
103 T
F SDA and SCL Fall
Time
100 kHz mode 300 ns
400 kHz mode 20 + 0.1 C
B 300 ns CB is specified to be from 10 to
400 pF
90 T
SU:STA Start Condition Setup
Time
100 kHz mode 4.7 s Only relevant for Repeated Start
condition
400 kHz mode 0.6 s
91 T
HD:STA Start Condition Hold
Time
100 kHz mode 4.0 s After this period, the first clock
pulse is generated
400 kHz mode 0.6 s
106 T
HD:DAT Data Input Hold Time 100 kHz mode 0 ns
400 kHz mode 0 0.9 s
107 T
SU:DAT Data Input Setup Time 100 kHz mode 250 ns (Note 2)
400 kHz mode 100 ns
92 T
SU:STO Stop Condition Setup
Time
100 kHz mode 4.7 s
400 kHz mode 0.6 s
109 T
AA Output Valid from
Clock
100 kHz mode 3500 ns (Note 1)
400 kHz mode ns
110 T
BUF Bus Free Time 100 kHz mode 4.7 s Time the bus must be free before
a new transmission can start
400 kHz mode 1.3 s
C
B Bus Capacitive Loading 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A fast mode (400 kHz) I
2
C bus device can be used in a standard mode (100 kHz) I
2
C bus system, but the requirement
that, T
SU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, T
R MAX. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I
2
C bus specification),
before the SCL line is released.