Datasheet

PIC16F87XA
DS39582C-page 190  2001-2013 Microchip Technology Inc.
TABLE 17-9: SPI MODE REQUIREMENTS
FIGURE 17-15: I
2
C BUS START/STOP BITS TIMING
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
70* T
SSL2SCH,
T
SSL2SCL
SS
 to SCK  or SCK  Input TCY ——ns
71* T
SCH SCK Input High Time (Slave mode) TCY + 20 — — ns
72* T
SCL SCK Input Low Time (Slave mode) TCY + 20 — — ns
73* T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — — ns
74* T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — — ns
75* T
DOR SDO Data Output Rise Time Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
76* T
DOF SDO Data Output Fall Time — 10 25 ns
77* T
SSH2DOZSS  to SDO Output High-Impedance 10 — 50 ns
78* T
SCR SCK Output Rise Time
(Master mode)
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79* T
SCF SCK Output Fall Time (Master mode) — 10 25 ns
80* T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after
SCK Edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
ns
81* T
DOV2SCH,
T
DOV2SCL
SDO Data Output Setup to SCK Edge T
CY ——ns
82* T
SSL2DOV SDO Data Output Valid after SS  Edge — — 50 ns
83* T
SCH2SSH,
T
SCL2SSH
SS
after SCK Edge 1.5 TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
91
93
SCL
SDA
Start
Condition
Stop
Condition
90
92