Datasheet
2001-2013 Microchip Technology Inc. DS39582C-page 19
PIC16F87XA
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Details
on page:
Bank 0
00h
(3)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
01h TMR0 Timer0 Module Register xxxx xxxx 55, 150
02h
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 30, 150
03h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
04h
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 31, 150
05h PORTA
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 43, 150
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 45, 150
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 47, 150
08h
(4)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 48, 150
09h
(4)
PORTE — — — — — RE2 RE1 RE0 ---- -xxx 49, 150
0Ah
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 30, 150
0Bh
(3)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
0Ch PIR1 PSPIF
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 26, 150
0Dh PIR2
—CMIF—EEIFBCLIF— —CCP2IF-0-0 0--0 28, 150
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 60, 150
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 60, 150
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57, 150
11h TMR2 Timer2 Module Register 0000 0000 62, 150
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 61, 150
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 79, 150
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 82, 82,
150
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 63, 150
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 63, 150
17h CCP1CON
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 64, 150
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 112, 150
19h TXREG USART Transmit Data Register 0000 0000 118, 150
1Ah RCREG USART Receive Data Register 0000 0000 118, 150
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 63, 150
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 63, 150
1Dh CCP2CON
— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 64, 150
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 133, 150
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
—ADON0000 00-0 127, 150
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.