Datasheet

 2001-2013 Microchip Technology Inc. DS39582C-page 183
PIC16F87XA
FIGURE 17-5: CLKO AND I/O TIMING
TABLE 17-4: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
10* T
OSH2CKLOSC1  to CLKO  — 75 200 ns (Note 1)
11* T
OSH2CKHOSC1  to CLKO  — 75 200 ns (Note 1)
12* T
CKR CLKO Rise Time — 35 100 ns (Note 1)
13* T
CKF CLKO Fall Time — 35 100 ns (Note 1)
14* T
CKL2IOVCLKO  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15* T
IOV2CKH Port In Valid before CLKO  TOSC + 200 — — ns (Note 1)
16* T
CKH2IOI Port In Hold after CLKO  0——ns(Note 1)
17* T
OSH2IOVOSC1  (Q1 cycle) to Port Out Valid — 100 255 ns
18* T
OSH2IOIOSC1  (Q2 cycle) to Port Input
Invalid (I/O in hold time)
Standard (F) 100 — — ns
Extended (LF) 200 — — ns
19* T
IOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns
20* T
IOR Port Output Rise Time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
21* T
IOF Port Output Fall Time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
22††* T
INP INT pin High or Low Time TCY ——ns
23††* T
RBP RB7:RB4 Change INT High or Low Time TCY ——ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKO output is 4 x T
OSC.