Datasheet
2001-2013 Microchip Technology Inc. DS39582C-page 141
PIC16F87XA
13.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The Comparator Voltage Reference Generator is a
16-tap resistor ladder network that provides a fixed
voltage reference when the comparators are in mode
‘
110’. A programmable register controls the function of
the reference generator. Register 13-1 lists the bit
functions of the CVRCON register.
As shown in Figure 13-1, the resistor ladder is seg-
mented to provide two ranges of CV
REF values and has
a power-down function to conserve power when the
reference is not being used. The comparator reference
supply voltage (also referred to as CV
RSRC) comes
directly from V
DD. It should be noted, however, that the
voltage at the top of the ladder is CV
RSRC – VSAT,
where V
SAT is the saturation voltage of the power
switch transistor. This reference will only be as
accurate as the values of CVRSRC and VSAT.
The output of the reference generator may be con-
nected to the RA2/AN2/V
REF-/CVREF pin. This can be
used as a simple D/A function by the user if a very high-
impedance load is used. The primary purpose of this
function is to provide a test path for testing the
reference generator function.
REGISTER 13-1: CVRCON CONTROL REGISTER (ADDRESS 9Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR
— CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 =CV
REF circuit powered on
0 =CV
REF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 =CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin
0 =CV
REF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin
bit 5 CVRR: Comparator V
REF Range Selection bit
1 = 0 to 0.75 CV
RSRC, with CVRSRC/24 step size
0 = 0.25 CV
RSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits 0 VR3:VR0 15
When CVRR = 1:
CV
REF = (VR<3:0>/ 24) (CVRSRC)
When CVRR = 0:
CV
REF = 1/4 (CVRSRC) + (VR3:VR0/ 32) (CVRSRC)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown