Information

MSSP MODULE
DS80131E-page 2 © 2006 Microchip Technology Inc.
Clarifications/Corrections to the Data
Sheets
1. Module: MSSP (SPI Mode)
The description of the operation of the CKE bit
(SSPSTAT<6>) is clarified. Please substitute the
description in Register 1, below, for all occurrences
of the existing text for the SSPSTAT register, bit 6
(new text in bold).
2. Module: MSSP (SPI Slave Mode)
The description of the operation of SPI Slave
mode is clarified as follows: the state of the clock
line (SCK) must match the polarity for the Idle state
before enabling the module.
The subsection of the “MSSP Module” chapter,
entitled “Slave Mode” (Subsection 3.6 in the
majority of data sheets, Subsection 3.5 in others),
is amended by adding the following paragraph to
the end of the existing text:
“Before enabling the module in SPI Slave mode,
the clock line must match the proper Idle state.
The clock line can be observed by reading the
SCK pin. The Idle state is determined by the CKP
bit (SSPCON1<4>) .”
REGISTER 1: SSPSTAT: MSSP STATUS REGISTER (EXCERPT)
Note: Items 1-3 apply to the Data Sheets for the
following devices:
• PIC16C717/770/771 (DS41120B)
• PIC16C773/774 (DS30275A)
• PIC16F872 (DS30221B)
• PIC16F873/874/876/877 (DS30292C)
• PIC16F873A/874A/876A/877A
(DS39582B)
• PIC17C752/756A/762/766 (DS30289B)
• PIC18C242/252/442/452 (DS39026C)
• PIC18C601/801 (DS39541A)
• PIC18C658/858 (DS30475A)
• PIC18F242/252/442/452 (DS39564B)
• PIC18F2220/2320/4220/4320
(DS39599C)
• PIC18F2439/2539/4439/4539
(DS30485A)
• PIC18F6520/6620/6720/8520/8620/
8720 (DS39609B)
• PIC18F6585/6680/8585/8680
(DS30491C)
Note: This text refers only to the operation of
the CKE bit in SPI mode; its operation
in I
2
C mode is unchanged. For those
data sheets that describe the SSPSTAT
register in separate locations for SPI
and I
2
C modes, this description applies
only to the register titled “SSPSTAT
Register (SPI Mode)”.
bit 6 CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>).