Datasheet

 2001 Microchip Technology Inc. DS30292C-page 71
PIC16F87X
9.1.2 SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the last
bit is latched, the interrupt flag bit SSPIF (PIR1<3>) is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
Note 1: When the SPI module is in Slave
mode with SS
pin control enabled
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = ’1’, then SS
pin control must be
enabled.
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7
bit6 bit5
bit4
bit3
bit2
bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS (optional)
SCK (CKP = 0)
SDI (SMP = 0)
SSPIF
bit7
bit6 bit5
bit4
bit3
bit2
bit1 bit0
SCK (CKP = 1)
SDO
bit7 bit0
SS