Datasheet
2001 Microchip Technology Inc. DS30292C-page 17
PIC16F87X
Bank 2
100h
(3)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
101h TMR0 Timer0 Module Register
xxxx xxxx 47
102h
(3)
PCL Program Counter’s (PC) Least Significant Byte 0000 0000 26
103h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18
104h
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 31
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
10Bh
(3)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
10Ch EEDATA EEPROM Data Register Low Byte
xxxx xxxx 41
10Dh EEADR EEPROM Address Register Low Byte
xxxx xxxx 41
10Eh EEDATH
— — EEPROM Data Register High Byte xxxx xxxx 41
10Fh EEADRH
— — — EEPROM Address Register High Byte xxxx xxxx 41
Bank 3
180h
(3)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
1111 1111 19
182h
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 26
183h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18
184h
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register
1111 1111 31
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
18Bh
(3)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
18Ch EECON1 EEPGD
— — — WRERR WREN WR RD x--- x000 41, 42
18Dh EECON2 EEPROM Control Register2 (not a physical register)
---- ---- 41
18Eh — Reserved maintain clear 0000 0000 —
18Fh — Reserved maintain clear 0000 0000 —
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Details
on
page:
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.