Datasheet

 2001 Microchip Technology Inc. DS30292C-page 173
PIC16F87X
FIGURE 15-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 15-20: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 15-5 for load conditions.
121
121
122
RC6/TX/CK
RC7/RX/DT
Pin
Pin
120
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
Standard(F)
——80 ns
Extended(LF) ——100 ns
121 Tckrf Clock out rise time and fall time
(Master mode)
Standard(F) ——45 ns
Extended(LF) ——50 ns
122 Tdtrf Data out rise time and fall time Standard(F) ——45 ns
Extended(LF) ——50 ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 15-5 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
125 TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup
time)
15 —— ns
126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 —— ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.