Datasheet
2001 Microchip Technology Inc. DS30292C-page 15
PIC16F87X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Details
on
page:
Bank 0
00h
(3)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
01h TMR0 Timer0 Module Register
xxxx xxxx 47
02h
(3)
PCL Program Counter (PC) Least Significant Byte 0000 0000 26
03h
(3)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18
04h
(3)
FSR Indirect Data Memory Address Pointer xxxx xxxx 27
05h PORTA
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 29
06h PORTB PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 31
07h PORTC PORTC Data Latch when written: PORTC pins when read
xxxx xxxx 33
08h
(4)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 35
09h
(4)
PORTE — — — — — RE2 RE1 RE0 ---- -xxx 36
0Ah
(1,3)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
0Bh
(3)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
0Ch PIR1 PSPIF
(3)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 22
0Dh PIR2
— (5) — EEIF BCLIF — — CCP2IF -r-0 0--0 24
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 52
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 52
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 51
11h TMR2 Timer2 Module Register
0000 0000 55
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 70, 73
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 67
15h CCPR1L Capture/Compare/PWM Register1 (LSB)
xxxx xxxx 57
16h CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx 57
17h CCP1CON
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 58
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0000 000x 96
19h TXREG USART Transmit Data Register
0000 0000 99
1Ah RCREG USART Receive Data Register
0000 0000 101
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB)
xxxx xxxx 57
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx 57
1Dh CCP2CON
— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58
1Eh ADRESH A/D Result Register High Byte
xxxx xxxx 116
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
— ADON 0000 00-0 111
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.