Datasheet

PIC16F87X
DS30292C-page 116 2001 Microchip Technology Inc.
11.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2T
AD wait is required before the next
acquisition is started. After this 2T
AD wait, acquisition
on the selected channel is automatically started. The
GO/DONE
bit can then be set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time seg-
ment has a minimum of T
CY and a maximum of TAD.
FIGURE 11-3: A/D CONVERSION TAD CYCLES
11.4.1 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with 0s. When an
A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
FIGURE 11-4: A/D RESULT JUSTIFICATION
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1
TAD2 TAD3
T
AD
4
TAD5
TAD6
T
AD
7 T
AD
8
T
AD
9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY to TAD
Conversion starts
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
10-bit Result
ADRESH ADRESL
0000 00
ADFM = 0
0
2 1 0 77
10-bit Result
ADRESH ADRESL
10-bit Result
0000 00
7
0 7 6 5 0
ADFM = 1
Right Justified
Left Justified