Datasheet
PIC16F87X
DS30292C-page 112 2001 Microchip Technology Inc.
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE
bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM
— — — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1: These channels are not available on PIC16F873/876 devices.
2: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
A = Analog input D = Digital I/O
PCFG3:
PCFG0
AN7
(1)
RE2
AN6
(1)
RE1
AN5
(1)
RE0
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
V
REF+VREF-
C
HAN/
Refs
(2)
0000 AAAAAAAAVDD VSS 8/0
0001 AAAAVREF+A A A RA3VSS 7/1
0010 DDDA A AAAVDD VSS 5/0
0011 DDDAVREF+A A A RA3VSS 4/1
0100 DDDD A DAAVDD VSS 3/0
0101 DDDDVREF+D A A RA3VSS 2/1
011x DDDD DDDDVDD VSS 0/0
1000 AAAAVREF+VREF-A A RA3RA2 6/2
1001 DDAA A AAAVDD VSS 6/0
1010 DDAAVREF+A A A RA3VSS 5/1
1011 DDAAVREF+VREF-A A RA3RA2 4/2
1100 DDDAVREF+VREF-A A RA3RA2 3/2
1101 DDDDVREF+VREF-A A RA3RA2 2/2
1110 DDDD DDDAVDD VSS 1/0
1111 DDDDVREF+VREF-D A RA3RA2 1/2