Datasheet
PIC16F872
DS30221C-page 82 © 2006 Microchip Technology Inc.
10.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (R
S) and the internal sampling
switch (R
SS) impedance directly affect the time
required to charge the capacitor C
HOLD. The sampling
switch (R
SS) impedance varies over the device voltage
(V
DD), Figure 10-2. The maximum recommended
impedance for analog sources is 10 kΩ. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
Equation 10-1 may be used to calculate the minimum
acquisition time. This equation assumes that 1/2 LSb
error is used (1024 steps for the A/D). The 1/2 LSb
error is the maximum error allowed for the A/D to meet
its specified resolution.
To calculate the minimum acquisition time, T
ACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
EQUATION 10-1: ACQUISITION TIME
FIGURE 10-2: ANALOG INPUT MODEL
TACQ
TC
TACQ
=
=
=
=
=
=
=
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
T
AMP + TC + TCOFF
2 μs + TC + [(Temperature -25°C)(0.05 μs/°C)]
C
HOLD (RIC + RSS + RS) In(1/2047) - 120 pF (1 kΩ + 7 kΩ + 10 kΩ) In(0.0004885)
16.47 μs
2 μs + 16.47 μs + [(50°C -25°C)(0.05 μs/°C)
19.72 μs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
CPIN
VA
R
S
ANx
5 pF
V
DD
VT = 0.6V
V
T = 0.6V
I
LEAKAGE
RIC ≤ 1k
Sampling
Switch
SS
R
SS
CHOLD
= DAC capacitance
V
SS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(kΩ)
VDD
= 120 pF
± 500 nA
Legend CPIN
VT
I LEAKAGE
RIC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions