Datasheet

PIC16F872
DS30221C-page 72 © 2006 Microchip Technology Inc.
FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE
9.2.15 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 9-18).
9.2.16 SLEEP OPERATION
While in SLEEP mode, the I
2
C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the SSP interrupt is enabled).
9.2.17 EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for T
BRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after T
BRG
Note: TBRG = one baud rate generator period.
T
BRG
TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
T
BRG
to setup STOP condition.
ACK
P
T
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
SCL
SDA
BRG overflow,
release SCL.
If SCL = 1, load BRG with
SSPADD<6:0> and start count
BRG overflow occurs,
release SCL. Slave device holds SCL low.
SCL = 1, BRG starts counting
clock high interval
SCL line sampled once every machine cycle (T
OSC • 4).
Hold off BRG until SCL is sampled high.
TBRG
TBRG
TBRG
to measure high time interval.