Datasheet

PIC16F872
DS30221C-page 56 © 2006 Microchip Technology Inc.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This, then, would give
waveforms for SPI communication as shown in
Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
•F
OSC/4 (or TCY)
•F
OSC/16 (or 4 • TCY)
•FOSC/64 (or 16 • TCY)
• Timer2 Output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
FIGURE 9-2: SPI MODE TIMING, MASTER MODE
9.1.2 SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
SCK (CKP = 0,
SDI (SMP = 0)
SSPIF
bit7
bit6 bit5
bit4
bit3
bit2
bit1 bit0
SDI (SMP = 1)
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
bit7
bit7 bit0
bit0
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
Note 1: When the SPI module is in Slave mode
with SS
pin control enabled
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = '1', then SS
pin control must be
enabled.