Datasheet

PIC16F872
DS30221C-page 28 © 2006 Microchip Technology Inc.
3.8 Operation While Code Protected
The PIC16F872 has two code protect mechanisms,
one bit for EEPROM Data memory and two bits for
FLASH Program memory. Data can be read and written
to the EEPROM Data memory regardless of the state
of the code protection bit, CPD. When code protection
is enabled, CPD cleared, external access via ICSP is
disabled regardless of the state of the program memory
code protect bits. This prevents the contents of
EEPROM Data memory from being read out of the
device.
The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instruc-
tions out of program memory. The PIC16F872 can
always read the values in program memory, regardless
of the state of the code protect bits. However, the state
of the code protect bits and the WRT bit will have differ-
ent effects on writing to program memory. Table 4-1
shows the effect of the code protect bits and the WRT
bit on program memory.
Once code protection has been enabled for either
EEPROM Data memory or FLASH Program memory,
only a full erase of the entire device will disable code
protection.
3.9 FLASH Program Memory Write
Protection
The configuration word contains a bit that write protects
the FLASH Program memory called WRT. This bit can
only be accessed when programming the device via
ICSP. Once write protection is enabled, only an erase
of the entire device will disable it. When enabled, write
protection prevents any writes to FLASH Program
memory. Write protection does not affect program
memory reads.
TABLE 3-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
TABLE 3-2: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Configuration Bits
Memory Location
Internal
Read
Internal
Write
ICSP Read ICSP Write
CP1 CP0 WRT
000 All program memory Yes No No No
001 All program memory Yes Yes No No
110 All program memory Yes No Yes Yes
111 All program memory Yes Yes Yes Yes
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh, 18Bh
INTCON GIE PEIE
TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Dh EEADR EEPROM Address Register, Low Byte xxxx xxxx uuuu uuuu
10Fh EEADRH
— — — EEPROM Address, High Byte xxxx xxxx uuuu uuuu
10Ch EEDATA EEPROM Data Register, Low Byte xxxx xxxx uuuu uuuu
10Eh EEDATH
— — EEPROM Data Register, High Byte xxxx xxxx uuuu uuuu
18Ch EECON1 EEPGD
— — — WRERR WREN WR RD x--- x000 x--- u000
18Dh EECON2 EEPROM Control Register2 (not a physical register) — —
8Dh PIE2
— (1) —EEIEBCLIE — — (1) -r-0 0--r -r-0 0--r
0Dh PIR2
— (1) —EEIFBCLIF — — (1) -r-0 0--r -r-0 0--r
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.