Datasheet

PIC16F872

2.2.2.7 PIR2 Register

The PIR2 register contains the flag bits for the CCP2

interrupt, the SSP bus collision interrupt and the

EEPROM write operation interrupt.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0

— reserved — EEIF BCLIF — — reserved

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6 Reserved: Always maintain this bit clear

bit 5 Unimplemented: Read as '0'

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred in the SSP, when configured for I

C Master mode

0 = No bus collision has occurred

bit 2-1 Unimplemented: Read as '0'

bit 0 Reserved: Always maintain this bit clear

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown