Datasheet

PIC16F872
DS30221C-page 16 © 2006 Microchip Technology Inc.
2.2.2.5 PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
REGISTER 2-5: PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
reserved ADIF reserved reserved SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Reserved: Always maintain these bits clear
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4 Reserved: Always maintain these bits clear
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI
- A transmission/reception has taken place
• I
2
C Slave
- A transmission/reception has taken place
•I
2
C Master
- A transmission/reception has taken place
- The initiated START condition was completed by the SSP module
- The initiated STOP condition was completed by the SSP module
- The initiated Restart condition was completed by the SSP module
- The initiated Acknowledge condition was completed by the SSP module
- A START condition occurred while the SSP module was idle (multi-master system)
- A STOP condition occurred while the SSP module was idle (multi-master system)
0 = No SSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown