Datasheet

PIC16F872
DS30221C-page 134 © 2006 Microchip Technology Inc.
TABLE 14-6: SPI MODE REQUIREMENTS
FIGURE 14-14: I
2
C BUS START/STOP BITS TIMING
TABLE 14-7: I
2
C BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol Characteristic Min Typ† Max Units Conditions
70* TssL2scH,
TssL2scL
SS
↓ to SCK↓ or SCK↑ Input TCY ——ns
71* TscH SCK Input High Time (Slave mode) T
CY + 20 — — ns
72* TscL SCK Input Low Time (Slave mode) T
CY + 20 — — ns
73* TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge 100 — — ns
74* TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge 100 — — ns
75* TdoR SDO Data Output Rise Time Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
76* TdoF SDO Data Output Fall Time — 10 25 ns
77* TssH2doZ SS↑ to SDO Output Hi-Impedance 10 — 50 ns
78* TscR SCK Output Rise Time (Master mode) Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79* TscF SCK Output Fall Time (Master mode) — 10 25 ns
80* TscH2doV,
TscL2doV
SDO Data Output Valid after SCK
Edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
ns
81* TdoV2scH,
TdoV2scL
SDO Data Output Setup to SCK Edge T
CY ——ns
82* TssL2doV SDO Data Output Valid after SS
↓ Edge — — 50 ns
83* TscH2ssH,
TscL2ssH
SS
↑ after SCK Edge 1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Parameter
No.
Symbol Characteristic Min Typ Max Units Conditions
90 T
SU:STA START condition 100 kHz mode 4700 — — ns Only relevant for Repeated
START condition
Setup time 400 kHz mode 600 — —
91 T
HD:STA START condition 100 kHz mode 4000 — — ns After this period, the first clock
pulse is generated
Hold time 400 kHz mode 600 — —
92 T
SU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 T
HD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note: Refer to Figure 14-3 for load conditions.
91
93
SCL
SDA
START
Condition
STOP
Condition
90
92