Datasheet

© 2006 Microchip Technology Inc. DS30221C-page 11
PIC16F872
Bank 2
100h
(2)
INDF Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
101h TMR0 Timer0 Module Register xxxx xxxx 35, 93
102h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93
103h
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12, 93
104h
(2)
FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31, 93
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
10Bh
(2)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93
10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 23, 94
10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 23, 94
10Eh EEDATH
— — EEPROM Data Register High Byte xxxx xxxx 23, 94
10Fh EEADRH
— — — EEPROM Address Register High Byte xxxx xxxx 23, 94
Bank 3
180h
(2)
INDF Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13, 94
182h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93
183h
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12, 93
184h
(2)
FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 31, 94
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
18Bh
(2)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93
18Ch EECON1 EEPGD
— — — WRERR WREN WR RD x--- x000 24, 94
18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- 23, 94
18Eh — Reserved; maintain clear 0000 0000 —
18Fh — Reserved; maintain clear 0000 0000 —
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Details
on
page:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.