PIC16F872 Data Sheet 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D © 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F872 28-Pin, 8-Bit CMOS FLASH Microcontroller with 10-bit A/D • Only 35 single word instructions to learn • All single cycle instructions except for program branches, which are two-cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • 2K x 14 words of FLASH Program Memory • 128 bytes of Data Memory (RAM) • 64 bytes of EEPROM Data Memory • Pinout compatible to the PIC16C72A • Interrupt capability (up to 10 sources) • Eight level deep hardware stack • Direct, Indirect and Relat
PIC16F872 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 3 2.0 Memory Organization.................................................................................................................................................................. 7 3.0 Data EEPROM and FLASH Program Memory ...............................................................
PIC16F872 1.0 DEVICE OVERVIEW This document contains device specific information about the PIC16F872 microcontroller. Additional information may be found in the PICmicro™ Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website.
PIC16F872 FIGURE 1-1: PIC16F872 BLOCK DIAGRAM 13 FLASH Program Memory Program Bus RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RAM File Registers 8 Level Stack (13-bit) 14 PORTA 8 Data Bus Program Counter RAM Addr (1) 9 PORTB Addr MUX Instruction reg Direct Addr 7 8 RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD Indirect Addr FSR reg STATUS reg 8 Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT 3 Power-up Timer Oscillator Start-up Timer Power-on
PIC16F872 TABLE 1-2: Pin Name OSC1/CLKI OSC1 PIC16F872 PINOUT DESCRIPTION Pin# I/O/P Type 9 I 10 O — Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. 1 I/P ST Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input.
PIC16F872 TABLE 1-2: PIC16F872 PINOUT DESCRIPTION (CONTINUED) Pin Name Pin# I/O/P Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. I/O TTL/ST(1) RB0/INT RB0 INT 21 RB1 22 I/O TTL Digital I/O. RB2 23 I/O TTL Digital I/O. RB3/PGM RB3 PGM 24 I/O TTL RB4 25 I/O TTL RB5 26 I/O TTL Digital I/O. External interrupt pin. Digital I/O. Low voltage ICSP programming enable pin. Digital I/O.
PIC16F872 2.0 MEMORY ORGANIZATION There are three memory blocks in the PIC16F872. The Program Memory and Data Memory have separate buses so that concurrent access can occur. Data memory is covered in this section; the EEPROM data memory and FLASH program memory blocks are detailed in Section 3.0. 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers.
PIC16F872 FIGURE 2-2: PIC16F872 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register File Address Indirect addr.
PIC16F872 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section. The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device.
PIC16F872 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page: Bank 1 80h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU 0000 0000 21, 93 81h OPTION_REG 82h(2) PCL 83h(2) STATUS 84h(2) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 31, 94 87h TRISC PORTC Data Direction Register 1111 1111 33, 94 IN
PIC16F872 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on: POR, BOR Bit 0 Details on page: Bank 2 100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 21, 93 xxxx xxxx 35, 93 101h TMR0 Timer0 Module Register 102h(2) PCL Program Counter (PC) Least Significant Byte 103h(2) STATUS 104h(2) FSR 105h RP1 RP0 TO 0000 0000 20, 93 PD Z DC C 0001
PIC16F872 2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F872 2.2.2.2 OPTION_REG Register Note: The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F872 2.2.2.3 INTCON Register Note: The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F872 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the individual enable bits for the peripheral interrupts.
PIC16F872 2.2.2.5 PIR1 Register Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
PIC16F872 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt.
PIC16F872 2.2.2.7 PIR2 Register Note: The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt. . REGISTER 2-7: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F872 2.2.2.8 PCON Register Note: The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 2-8: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16F872 2.3 2.3.2 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F872 2.5 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-1: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR.
PIC16F872 NOTES: DS30221C-page 22 © 2006 Microchip Technology Inc.
PIC16F872 3.0 DATA EEPROM AND FLASH PROGRAM MEMORY The Data EEPROM and FLASH Program Memory are readable and writable during normal operation over the entire VDD range. These operations take place on a single byte for Data EEPROM memory and a single word for Program memory. A write operation causes an erase-then-write operation to take place on the specified byte or word. A bulk erase operation may not be issued from user code (which includes removing code protection).
PIC16F872 Write operations have two control bits, WR and WREN, and two status bits, WRERR and EEIF. The WREN bit is used to enable or disable the write operation. When WREN is clear, the write operation will be disabled. Therefore, the WREN bit must be set before executing a write operation. The WR bit is used to initiate the write operation. It also is automatically cleared at the end of the write operation.
PIC16F872 3.2 Reading the EEPROM Data Memory Reading EEPROM Data memory only requires that the desired address to access be written to the EEADR register and clear the EEPGD bit. After the RD bit is set, data will be available in the EEDATA register on the very next instruction cycle. EEDATA will hold this value until another read operation is initiated or until it is written by firmware. The steps to reading the EEPROM Data Memory are: 1. 2. 3. 4. Write the address to EEDATA.
PIC16F872 3.4 Reading the FLASH Program Memory Reading FLASH Program memory is much like that of EEPROM Data memory, only two NOP instructions must be inserted after the RD bit is set. These two instruction cycles that the NOP instructions execute will be used by the microcontroller to read the data out of program memory and insert the value into the EEDATH:EEDATA registers. Data will be available following the second NOP instruction.
PIC16F872 The steps to write to program memory are: 1. 2. 3. 4. 5. 6. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the memory size of the device. Write the 14-bit data value to be programmed in the EEDATH:EEDATA registers. Set the EEPGD bit to point to FLASH Program memory. Set the WREN bit to enable program operations. Disable interrupts (if enabled).
PIC16F872 3.8 Operation While Code Protected The PIC16F872 has two code protect mechanisms, one bit for EEPROM Data memory and two bits for FLASH Program memory. Data can be read and written to the EEPROM Data memory regardless of the state of the code protection bit, CPD. When code protection is enabled, CPD cleared, external access via ICSP is disabled regardless of the state of the program memory code protect bits. This prevents the contents of EEPROM Data memory from being read out of the device.
PIC16F872 4.0 I/O PORTS FIGURE 4-1: The PIC16F872 provides three general purpose I/O ports. Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Data Bus WR Port BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Latch D Q CK Q VDD P Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual (DS33023).
PIC16F872 TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input.
PIC16F872 4.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= ‘1’) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F872 TABLE 4-3: Name PORTB FUNCTIONS Bit# Buffer Function RB0/INT bit0 TTL/ST(1) RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3/PGM bit3 TTL Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up.
PIC16F872 4.3 PORTC and the TRISC Register PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= ‘1’) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= ‘0’) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 4-5).
PIC16F872 TABLE 4-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM output. RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes.
PIC16F872 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2.
PIC16F872 5.2 Using Timer0 with an External Clock Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 5-1). When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.
PIC16F872 TABLE 5-1: Address 01h,101h REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 Module Register GIE PEIE OPTION_REG RBPU INTEDG Value on all other resets xxxx xxxx uuuu uuuu TMR0IE INTE T0CS Value on: POR, BOR T0SE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u PSA PS0 PS2 PS1 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
PIC16F872 NOTES: DS30221C-page 38 © 2006 Microchip Technology Inc.
PIC16F872 6.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
PIC16F872 6.1 Timer1 Operation in Timer Mode 6.2 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. FIGURE 6-1: Timer1 Counter Operation Timer1 may operate in either a Synchronous or an Asynchronous mode, depending on the setting of the TMR1CS bit.
PIC16F872 6.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1).
PIC16F872 TABLE 6-2: Address REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on: POR, BOR Value on all other RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh, INTCON 10Bh, 18Bh GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0Ch PIR1 (3) ADIF (3) (3) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 8Ch PIE1 (3) ADIE (3) (3) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 R
PIC16F872 7.0 TIMER2 MODULE Register 7-1 shows the Timer2 Control register. Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).
PIC16F872 7.1 Timer2 Prescaler and Postscaler 7.2 The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device RESET (POR, MCLR Reset, WDT Reset or BOR) Output of TMR2 The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock. TMR2 is not cleared when T2CON is written.
PIC16F872 8.0 CAPTURE/COMPARE/PWM MODULE The Capture/Compare/PWM (CCP) module contains a 16-bit register, which can operate as a: Additional information on CCP modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) and in Application Note (AN594), “Using the CCP Modules” (DS00594). TABLE 8-1: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register The timer resources used by the module are shown in Table 8-1.
PIC16F872 8.1 8.1.2 Capture Mode TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. • • • • 8.1.
PIC16F872 8.2 8.2.1 Compare Mode CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: Note: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. FIGURE 8-2: 8.2.
PIC16F872 8.3 8.3.1 PWM Mode (PWM) In Pulse Width Modulation mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F872 8.3.3 SETUP FOR PWM OPERATION 3. The following steps should be taken when configuring the CCP module for PWM operation: 4. 1. 5. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 8-4: Address Make the CCP1 pin an output by clearing the TRISC<2> bit.
PIC16F872 NOTES: DS30221C-page 50 © 2006 Microchip Technology Inc.
PIC16F872 9.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F872 REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h) R/W-0 SMP R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2C Master or Slave mode: 1= Slew rate control disabled for Standard Speed mode (100 kHz and
PIC16F872 REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS: 14h) R/W-0 WCOL bit 7 bit 7 bit 6 bit 5 bit 4 bit 3-0 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 WCOL: Write Collision Detect bit Master mode: 1 = A write to SSPBUF was attempted while the I2C conditions were not valid 0 = No collision Slave mode: 1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: R
PIC16F872 REGISTER 9-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS: 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from
PIC16F872 9.1 SPI Mode FIGURE 9-1: The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported.
PIC16F872 The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This, then, would give waveforms for SPI communication as shown in Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • FOSC/4 (or TCY) FOSC/16 (or 4 • TCY) FOSC/64 (or 16 • TCY) Timer2 Output/2 FIGURE 9-2: This allows a maximum bit clock frequency (at 20 MHz) of 5.0 MHz.
PIC16F872 FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit6 bit7 SDO bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit3 bit4 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 9-1: Address REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 0Bh, 8Bh, INTCON 10Bh, 18Bh GIE PEIE 0Ch PIR1 (1) ADIF
PIC16F872 9.2 MSSP I 2C Operation The MSSP module in I 2C mode, fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Refer to Application Note (AN578), "Use of the SSP Module in the I 2C Multi-Master Environment.
PIC16F872 There are certain conditions that will cause the MSSP module not to give this ACK pulse. These are if either (or both): a) b) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. If the BF bit is set, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF and SSPOV are set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV.
PIC16F872 TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV SSPSR → SSPBUF Generate ACK Pulse 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 Yes No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 9.2.1.3 Slave Transmission An SSP interrupt is generated for each data transfer byte.
PIC16F872 I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) FIGURE 9-7: R/W = 1 ACK Receiving Address SDA SCL A7 A6 1 2 Data in sampled S A5 A4 A3 A2 A1 3 4 5 6 7 D7 8 9 R/W = 0 Not ACK Transmitting Data 1 SCL held low while CPU responds to SSPIF D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is written in software From SSP Interrupt Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to
PIC16F872 9.2.3 SLEEP OPERATION 9.2.4 While in SLEEP mode, the I2C module can receive addresses or data. When an address match or complete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). A RESET disables the SSP module and terminates the current transfer.
PIC16F872 9.2.5 MASTER MODE The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (an SSP Interrupt will occur if enabled): Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is IDLE, with both the S and P bits clear.
PIC16F872 9.2.7 I2C MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. Once Master mode is enabled, the user has six options. • Assert a START condition on SDA and SCL. • Assert a Repeated START condition on SDA and SCL. • Write to the SSPBUF register, initiating transmission of data/address. • Generate a STOP condition on SDA and SCL. • Configure the I2C port to receive data.
PIC16F872 FIGURE 9-11: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL allowed to transition high SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements (on Q2 and Q4 cycles) BRG Value 03h 01h 00h (hold off) I2C MASTER MODE START CONDITION TIMING Note: To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>).
PIC16F872 9.2.10 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode), or eight bits of data (7-bit mode).
PIC16F872 9.2.11 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or either half of a 10-bit address, is accomplished by simply writing a value to SSPBUF register. This action will set the buffer full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time spec).
DS30221C-page 68 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After START condition SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from SSP interrupt 2 D6 Transmitting data
PIC16F872 9.2.12 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: The SSP module must be in an IDLE state before the RCEN bit is set, or the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/ low to high), and data is shifted into the SSPSR.
DS30221C-page 70 S ACKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1, while CPU responds to SSPIF SSPIF SCL SDA 2 1 A4 4 A5 3 5 A3 Cleared in software A6 6 A2 Transmit Address to Slave A7 7 A1 8 9 R/W = 1 ACK ACK from slave 2 D6 3 D5 5 D3 6 D2 7 D1 8 D0 9 ACK 2 D6 3 D5 4 D4 5 D3 6 D2 Receiving Data from Slave 7 D1 Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK
PIC16F872 9.2.13 ACKNOWLEDGE SEQUENCE TIMING sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off, and the SSP module then goes into IDLE mode (Figure 9-16). An Acknowledge sequence is enabled by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>).
PIC16F872 FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition. Note: TBRG = one baud rate generator period. 9.2.15 CLOCK ARBITRATION 9.2.
PIC16F872 9.2.18 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA, by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', a bus collision has taken place.
PIC16F872 9.2.18.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the START condition (Figure 9-20). SCL is sampled low before SDA is asserted low. (Figure 9-21). b) During a START condition, both the SDA and the SCL pins are monitored.
PIC16F872 FIGURE 9-21: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, Bus collision occurs. Set BCLIF. BCLIF Interrupts cleared in software S '0' '0' SSPIF '0' '0' FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA TBRG SDA pulled low by other master.
PIC16F872 9.2.18.2 Bus Collision During a Repeated START Condition SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time. During a Repeated START condition, a bus collision occurs if: a) b) If, however, SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs.
PIC16F872 9.2.18.3 Bus Collision During a STOP Condition The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0'.
PIC16F872 9.3 Connection Considerations for I2C Bus For standard mode I2C bus devices, the values of resistors Rp and Rs in Figure 9-27 depend on the following parameters: VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 = 1.7 kΩ. VDD, as a function of Rp, is shown in Figure 9-27. The desired noise margin of 0.1 VDD for the low level limits the maximum value of Rs. Series resistors are optional and used to improve ESD susceptibility.
PIC16F872 10.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: The Analog-to-Digital (A/D) Converter module has five input channels. The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation. The A/D conversion of the analog input signal results in a corresponding 10-bit digital number.
PIC16F872 REGISTER 10-2: ADCON1 REGISTER (ADDRESS: 9Fh) U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
PIC16F872 The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 10-1. 2. 3. 4. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC16F872 10.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), Figure 10-2.
PIC16F872 10.2 Selecting the A/D Conversion Clock 10.3 The ADCON1, and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12TAD per 10-bit conversion. The source of the A/D conversion clock is software selected.
PIC16F872 10.4 A/D Conversions In Figure 10-3, after the GO bit is set, the first time segment has a minimum of TCY and a maximum of TAD. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers).
PIC16F872 10.5 A/D Operation During SLEEP The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRES register.
PIC16F872 NOTES: DS30221C-page 86 © 2006 Microchip Technology Inc.
PIC16F872 11.0 SPECIAL FEATURES OF THE CPU The PIC16F872 microcontroller has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16F872 REGISTER 11-1: R/P-1 CP1 R/P-1 CP0 CONFIGURATION WORD (ADDRESS: 2007h)(1) R/P-1 U-0 DEBUG — R/P-1 R/P-1 R/P-1 WRT CPD LVP R/P-1 R/P-1 R/P-1 BODEN CP1 CP0 R/P-1 R/P-1 R/P-1 bit13 bit 13-12 bit 5-4 R/P-1 PWRTE WDTE F0SC1 F0SC0 bit0 CP1:CP0: FLASH Program Memory Code Protection bits(2) 11 = Code protection off 10 = Not supported 01 = Not supported 00 = All memory code protected bit 11 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general
PIC16F872 11.2 FIGURE 11-2: Oscillator Configurations 11.2.1 OSCILLATOR TYPES The PIC16F872 can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 11.2.2 OSC1 Clock from Ext.
PIC16F872 TABLE 11-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Cap. Range C1 Cap. Range C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF 11.2.3 For timing insensitive applications, the “RC” device option offers additional cost savings.
PIC16F872 11.3 Reset The PIC16F872 differentiates between various kinds of RESET: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) A simplified block diagram of the On-Chip Reset circuit is shown in Figure 11-4. Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET.
PIC16F872 11.4 Power-on Reset (POR) 11.7 A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit.
PIC16F872 TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx --
PIC16F872 TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt TMR1L xxxx xxxx uuuu uuuu uuuu uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu T1CON --00 0000 --uu uuuu --uu uuuu TMR2 0000 0000 0000 0000 uuuu uuuu T2CON -000 0000 -000 0000 -uuu uuuu SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 0000 0000 0000 0000 uuuu uuuu CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON -
PIC16F872 FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET © 2006 Microchip Technology Inc.
PIC16F872 FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-8: SLOW RISETIME (MCLR TIED TO VDD VIA RC NETWORK) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30221C-page 96 © 2006 Microchip Technology Inc.
PIC16F872 11.10 Interrupts The PIC16F872 has 10 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts or disables (if cleared) all interrupts.
PIC16F872 11.10.1 INT INTERRUPT 11.10.3 External interrupt on the RB0/INT pin is edge triggered, either rising if bit INTEDG (OPTION_REG<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F872 11.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin.
PIC16F872 11.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F872 FIGURE 11-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC PC+1 Inst(PC) = SLEEP Inst(PC - 1) PC+2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dumm
PIC16F872 11.17 In-Circuit Serial Programming PIC16F872 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
PIC16F872 12.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode which specifies the instruction type, and one or more operands which further specify the operation of the instruction.
PIC16F872 TABLE 12-2: PIC16F872 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W t
PIC16F872 12.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW Syntax: [ label ] BCF Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: (W) + k → (W) Status Affected: C, DC, Z Operation: 0 → (f) Description: The contents of the W register are added to the eight-bit literal 'k' and the result is placed in the W register. Status Affected: None Description: Bit 'b' in register 'f' is cleared.
PIC16F872 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Operation: Status Affected: None 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16F872 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register.
PIC16F872 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: No operation Operation: (f) → (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected.
PIC16F872 RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
PIC16F872 SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Operation: (W) .XOR. (f) → (destination) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in the W register.
PIC16F872 13.
PIC16F872 13.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC16F872 13.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices.
PIC16F872 13.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X ! ! ! ! ! ! © 2006 Microchip Technology Inc. ! ! ! † † ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! MCP2510 * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
PIC16F872 NOTES: DS30221C-page 116 © 2006 Microchip Technology Inc.
PIC16F872 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.
PIC16F872 FIGURE 14-1: PIC16F872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 20 MHz Frequency FIGURE 14-2: PIC16LF872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.2 V Equation 2 2.5 V 2.0 V Equation 1 4 MHz 10 MHz 20 MHz Frequency Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz; VDDAPPMIN = 2.2V - 3.0V Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN - 3.0V) + 10 MHz; VDDAPPMIN = 3.0V - 4.
PIC16F872 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial PIC16F872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Param Symbol No.
PIC16F872 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) (Continued) PIC16LF872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial PIC16F872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Param Symbol No.
PIC16F872 14.2 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section 14.1) DC CHARACTERISTICS Param No. Sym Min Typ† Max Units VSS VSS VSS VSS VSS - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V ≤ VDD ≤ 5.5V VSS -0.5 - 0.
PIC16F872 14.2 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section 14.1) DC CHARACTERISTICS Param No. Sym Min Typ† Max Units D080 Output Low Voltage I/O ports - - 0.6 V D083 OSC2/CLKOUT (RC osc config) - - 0.
PIC16F872 14.3 DC Characteristics: PIC16F872 (Extended) PIC16F872 (Extended) Param No. Symbol VDD D001 D001A D001A D002 VDR D003 VPOR D004 SVDD D005 VBOR Characteristic/ Device Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Min Typ† Max Units Conditions Supply Voltage V V V V LP, XT, RC osc configuration HS osc configuration BOR enabled, FMAX = 14 MHz(7) 1.5 5.5 5.5 5.5 — — VSS — V See section on Power-on Reset for details 0.
PIC16F872 14.4 DC Characteristics: PIC16F872 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Operating voltage VDD range as described in DC specification (Section 14.1) DC CHARACTERISTICS Param No. Sym Min Typ† Max Units Vss Vss Vss VSS VSS - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V ≤ VDD ≤ 5.5V Vss -0.5 - 0.3VDD 0.6 V V For entire VDD range for VDD = 4.5 to 5.5V - VDD VDD V V 4.5V ≤ VDD ≤ 5.
PIC16F872 14.4 DC Characteristics: PIC16F872 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Operating voltage VDD range as described in DC specification (Section 14.1) DC CHARACTERISTICS Param No. Sym VOL D080A D083A VOH D090A D092A D150* VOD D100 COSC2 D101 CIO D102 CB D120 D121 ED VDRW D122 TDEW D130 EP D131 VPR D132A Characteristic Min Max Units 0.6 0.6 V V IOL =2.5 mA, VDD = 4.5V IOL = 1.2 mA, VDD = 4.
PIC16F872 14.5 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F872 FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 14-1: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC Characteristic External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 TCY 3 TosL, TosH Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time Min Typ† Max Units DC DC DC DC DC 0.
PIC16F872 FIGURE 14-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 14-3 for load conditions. TABLE 14-2: Param No.
PIC16F872 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 14-3 for load conditions. FIGURE 14-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 14-3: Parameter No.
PIC16F872 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 14-3 for load conditions. TABLE 14-4: Param No.
PIC16F872 FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 14-3 for load conditions. TABLE 14-5: Param No.
PIC16F872 FIGURE 14-10: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 14-3 for load conditions. FIGURE 14-11: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 14-3 for load conditions.
PIC16F872 FIGURE 14-12: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 14-3 for load conditions. FIGURE 14-13: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 14-3 for load conditions.
PIC16F872 TABLE 14-6: Param No.
PIC16F872 FIGURE 14-15: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 14-3 for load conditions. TABLE 14-8: Param No. 100 I2C BUS DATA REQUIREMENTS Sym THIGH Characteristic Clock High Time Min Max Units 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.
PIC16F872 TABLE 14-9: Param No. A/D CONVERTER CHARACTERISTICS: PIC16F872 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LF872 (COMMERCIAL, INDUSTRIAL) Sym Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.
PIC16F872 FIGURE 14-16: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 ... 7 ... 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 14-10: A/D CONVERSION REQUIREMENTS Param No. 130 Sym TAD Characteristic A/D Clock Period Min Typ† Max Units Standard(F) 1.
PIC16F872 NOTES: DS30221C-page 138 © 2006 Microchip Technology Inc.
PIC16F872 15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F872 FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.4 5.5V 1.2 5.0V IDD (mA) 1.0 4.5V 4.0V 0.8 3.5V 0.6 3.0V 2.5V 0.4 2.2V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 15-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) IDD (mA) 1.8 1.
PIC16F872 FIGURE 15-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 80 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 70 5.0V 60 4.5V 50 IDD IDD(μA) (uA) 4.0V 3.5V 40 3.0V 30 2.5V 2.2V 20 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 15-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 110 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 100 5.5V 5.0V 90 80 4.
PIC16F872 FIGURE 15-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25°C) 4.0 3.3kΩ 3.5 3.0 5.1kΩ Freq (MHz) 2.5 2.0 10kΩ 1.5 1.0 0.5 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 15-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25°C) 2.0 1.8 3.3kΩ 1.6 1.4 5.1kΩ Freq (MHz) 1.2 1.0 0.8 10kΩ 0.6 0.4 0.2 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 VDD (V) DS30221C-page 142 © 2006 Microchip Technology Inc.
PIC16F872 FIGURE 15-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25°C) 1.0 0.9 3.3kΩ 0.8 0.7 5.1kΩ Freq (MHz) 0.6 0.5 0.4 10kΩ 0.3 0.2 0.1 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 15-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max (125C) (125°C) 10 IPD (μA) (85°C) Max (85C) 1 0.1 Typ Typ (25°C) (25C) 0.01 2.
PIC16F872 FIGURE 15-11: ΔIBOR vs. VDD OVER TEMPERATURE 1.2 Note: Device current in RESET depends on oscillator mode, frequency and circuit. Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.0 Max MaxRESET Reset ΔIBOR (mA) 0.8 0.6 Typ TypRESET Reset (25°C) (25C) Indeterminate State 0.4 Device Device in in SLEEP Sleep Device Devicein inRESET Reset 0.2 Max MaxSLEEP Sleep Typ (25°C) TypSLEEP Sleep (25C) 0.0 2.0 2.2 2.5 3.0 3.5 4.0 4.
PIC16F872 FIGURE 15-13: TYPICAL AND MAXIMUM ΔIWDT vs. VDD OVER TEMPERATURE 14 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 12 10 ΔIWDT (μA) Max Max(125°C) (125C) 8 Typ Typ (25°C) (25C) 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD(V) FIGURE 15-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs.
PIC16F872 FIGURE 15-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C) 50 45 35 WDT Period (ms) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 125°C 125C 40 85°C 85C 30 25°C 25C 25 20 -40°C -40C 15 10 5 0 2.0 2.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=5V, -40°C TO +125°C) 5.0 Max (-40C) (-40°C) 4.5 Typ (25°C) (25C) VOH (V) 4.0 3.
PIC16F872 FIGURE 15-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=3V, -40°C TO +125°C) 3.0 Max Max (-40°C) (-40C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 2.5 Typ Typ(25°C) (25C) 2.0 VOH (V) Min Min(125°C) (125C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 15-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=5V, -40°C TO 125°C) 2.0 1.
PIC16F872 FIGURE 15-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=3V, -40°C TO +125°C) 3.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 2.5 VOL (V) 2.0 1.5 Max Max (125°C) (125C) 1.0 Typ (25°C) (25C) 0.5 Min Min (-40°C) (-40C) 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 15-20: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO +125°C) 1.
PIC16F872 FIGURE 15-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.5 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 3.5 Max High VIN (V) 3.0 Min High 2.5 2.0 Max Low 1.5 Min Low 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO +125°C) 3.
PIC16F872 NOTES: DS30221C-page 150 © 2006 Microchip Technology Inc.
PIC16F872 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 28-Lead SPDIP Example PIC16F872/SP e3 0610017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC16F872 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN 28 NOM MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.
PIC16F872 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MAX MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.
PIC16F872 28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 1 n A c A2 φ A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width A A2 A1 E E1 D L c φ B MIN .065 .002 .295 .197 .
PIC16F872 APPENDIX A: REVISION HISTORY Version Date Revision Description A 11/99 This is a new data sheet (Preliminary). However, these devices are similar to the PIC16C72A devices found in the PIC16C62B/72A Data Sheet (DS35008). B C 12/01 9/06 Final version of data sheet. Includes DC and AC characteristics graphs and updated electrical specifications. Packaging diagrams updated. © 2006 Microchip Technology Inc.
PIC16F872 NOTES: DS30221C-page 156 © 2006 Microchip Technology Inc.
PIC16F872 INDEX A A/D ..................................................................................... 79 Acquisition Requirements .......................................... 82 ADCON0 Register ..................................................... 79 ADCON1 Register ..................................................... 79 ADIF Bit ..................................................................... 81 ADRESH Register ..................................................... 79 ADRESL Register .............
PIC16F872 Code Protection ........................................................ 87, 101 Compare Mode CCP Pin Configuration ............................................... 47 Timer1 Mode Selection .............................................. 47 Computed GOTO ............................................................... 20 Configuration Bits .............................................................. 87 Configuration Word ............................................................
PIC16F872 MOVF ...................................................................... 108 MOVLW ................................................................... 108 MOVWF ................................................................... 108 NOP ......................................................................... 108 RETFIE .................................................................... 108 RETLW .................................................................... 108 RETURN ..................
PIC16F872 P P Bit STOP Bit (P) .............................................................. 52 Packaging ............................................................... 151–154 PCL Register ..........................................................9, 10, 20 PCLATH Register ......................................................... 9, 20 PCON Register .....................................................10, 19, 92 BOR Bit ...................................................................... 19 POR Bit ....
PIC16F872 RESET ........................................................................ 87, 91 RESET Conditions for All Registers .......................... 93 RESET Conditions for PCON Register ...................... 93 RESET Conditions for Program Counter ................... 93 RESET Conditions for Special Registers .................. 93 RESET Conditions for STATUS Register .................. 93 RESET Brown-out Reset (BOR). See Brown-out Reset (BOR) MCLR Reset. See MCLR Power-on Reset (POR).
PIC16F872 Bus Collision During START Condition (SCL = 0) ................................................... 75 Bus Collision During START Condition (SDA Only) ................................................ 74 Capture/Compare/PWM .......................................... 131 CLKOUT and I/O ..................................................... 128 External Clock .......................................................... 127 First START Bit Timing ..............................................
PIC16F872 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F872 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F872 PIC16F872 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X PART NO. Device Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F87X(1), PIC16F87XT(2);VDD range 4.0V to 5.5V PIC16LF87X(1), PIC16LF87XT(2 );VDD range 2.0V to 5.
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.
