Datasheet
Table Of Contents
- High Performance RISC CPU:
- Peripheral Features:
- CMOS Technology:
- Pin Diagram
- Special Microcontroller Features:
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Memory Organization
- 2.1 Program Memory Organization
- 2.2 Data Memory Organization
- 2.3 PCL and PCLATH
- 2.4 Program Memory Paging
- 2.5 Indirect Addressing, INDF and FSR Registers
- 3.0 Data EEPROM and Flash Program Memory
- 3.1 EECON1 and EECON2 Registers
- 3.2 Reading the EEPROM Data Memory
- 3.3 Writing to the EEPROM Data Memory
- 3.4 Reading the FLASH Program Memory
- 3.5 Writing to the FLASH Program Memory
- 3.6 Write Verify
- 3.7 Protection Against Spurious Writes
- 3.8 Operation While Code Protected
- 3.9 FLASH Program Memory Write Protection
- 4.0 I/O Ports
- 5.0 Timer0 Module
- 6.0 Timer1 Module
- Register 6-1: T1CON: Timer1 Control Register (Address 10h)
- 6.1 Timer1 Operation in Timer Mode
- 6.2 Timer1 Counter Operation
- 6.3 Timer1 Operation in Synchronized Counter Mode
- 6.4 Timer1 Operation in Asynchronous Counter Mode
- 6.5 Timer1 Oscillator
- 6.6 Resetting Timer1 using a CCP Trigger Output
- 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L)
- 6.8 Timer1 Prescaler
- 7.0 Timer2 Module
- 8.0 Capture/Compare/PWM Module
- 9.0 Master Synchronous Serial Port (MSSP) Module
- Register 9-1: SSPSTAT: Sync Serial Port Status Register (Address: 94h)
- Register 9-2: SSPCON: Sync Serial Port Control Register (Address: 14h)
- Register 9-3: SSPCON2: Sync Serial Port Control Register2 (Address: 91h)
- 9.1 SPI Mode
- 9.2 MSSP I2C Operation
- FIGURE 9-5: I2C Slave Mode Block Diagram
- 9.2.1 SLAVE Mode
- 9.2.2 General Call Address Support
- 9.2.3 Sleep Operation
- 9.2.4 Effects of a Reset
- 9.2.5 Master Mode
- 9.2.6 Multi-master Mode
- 9.2.7 I2C Master Mode Support
- 9.2.8 Baud Rate Generator
- 9.2.9 I2C Master Mode Start Condition Timing
- 9.2.10 I2C Master Mode Repeated Start Condition Timing
- 9.2.11 I2C Master Mode Transmission
- 9.2.12 I2C Master Mode Reception
- 9.2.13 Acknowledge Sequence Timing
- 9.2.14 Stop Condition Timing
- 9.2.15 Clock Arbitration
- 9.2.16 Sleep Operation
- 9.2.17 Effects of a Reset
- 9.2.18 Multi -Master Communication, Bus Collision, And Bus Arbitration
- 9.3 Connection Considerations for I2C Bus
- 10.0 Analog-to-Digital Converter (A/D) Module
- 11.0 Special Features of the CPU
- 11.1 Configuration Bits
- 11.2 Oscillator Configurations
- 11.3 Reset
- 11.4 Power-on Reset (POR)
- 11.5 Power-up Timer (PWRT)
- 11.6 Oscillator Start-up Timer (OST)
- 11.7 Brown-out Reset (BOR)
- 11.8 Time-out Sequence
- 11.9 Power Control/Status Register (PCON)
- TABLE 11-3: Time-out in Various Situations
- TABLE 11-4: Status Bits and Their Significance
- TABLE 11-5: Reset Condition for Special Registers
- TABLE 11-6: Initialization Conditions for all Registers
- FIGURE 11-5: Time-out Sequence on Power-up (MCLR Tied to Vdd VIA RC NETWORK)
- FIGURE 11-6: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1
- FIGURE 11-7: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2
- FIGURE 11-8: Slow RiseTime (MCLR Tied to Vdd VIA RC NETWORK)
- 11.10 Interrupts
- 11.11 Context Saving During Interrupts
- 11.12 Watchdog Timer (WDT)
- 11.13 Power-down Mode (SLEEP)
- 11.14 In-Circuit Debugger
- 11.15 Program Verification/Code Protection
- 11.16 ID Locations
- 11.17 In-Circuit Serial Programming
- 11.18 Low Voltage ICSP Programming
- 12.0 Instruction Set Summary
- 13.0 Development Support
- 13.1 MPLAB Integrated Development Environment Software
- 13.2 MPASM Assembler
- 13.3 MPLAB C17 and MPLAB C18 C Compilers
- 13.4 MPLINK Object Linker/ MPLIB Object Librarian
- 13.5 MPLAB SIM Software Simulator
- 13.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
- 13.7 ICEPIC In-Circuit Emulator
- 13.8 MPLAB ICD In-Circuit Debugger
- 13.9 PRO MATE II Universal Device Programmer
- 13.10 PICSTART Plus Entry Level Development Programmer
- 13.11 PICDEM 1 Low Cost PICmicro Demonstration Board
- 13.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
- 13.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
- 13.14 PICDEM 17 Demonstration Board
- 13.15 KeeLoq Evaluation and Programming Tools
- 14.0 Electrical Characteristics
- FIGURE 14-1: PIC16F872 Voltage-Frequency Graph
- FIGURE 14-2: PIC16LF872 Voltage-Frequency Graph
- 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial)
- 14.2 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial)
- 14.3 DC Characteristics: PIC16F872 (Extended)
- 14.4 DC Characteristics: PIC16F872 (Extended)
- 14.5 Timing Parameter Symbology
- FIGURE 14-3: Load Conditions
- FIGURE 14-4: External Clock Timing
- TABLE 14-1: External Clock Timing Requirements
- FIGURE 14-5: CLKOUT and I/O Timing
- TABLE 14-2: CLKOUT and I/O Timing Requirements
- FIGURE 14-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- FIGURE 14-7: Brown-out Reset Timing
- TABLE 14-3: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and brown-out reset...
- FIGURE 14-8: Timer0 and Timer1 External Clock Timings
- TABLE 14-4: Timer0 and Timer1 External Clock Requirements
- FIGURE 14-9: Capture/Compare/PWM Timings
- TABLE 14-5: Capture/Compare/PWM Requirements
- FIGURE 14-10: SPI Master Mode Timing (CKE=0, smp = 0)
- FIGURE 14-11: SPI Master Mode Timing (CKE=1, SMP = 1)
- FIGURE 14-12: SPI Slave Mode Timing (CKE=0)
- FIGURE 14-13: SPI Slave Mode Timing (CKE=1)
- TABLE 14-6: SPI Mode requirements
- FIGURE 14-14: I2C Bus Start/Stop Bits Timing
- TABLE 14-7: I2C Bus Start/Stop Bits Requirements
- FIGURE 14-15: I2C Bus Data Timing
- TABLE 14-8: I2C Bus Data Requirements
- TABLE 14-9: A/D Converter Characteristics: PIC16F872 (Commercial, Industrial, extended) PIC16LF87...
- FIGURE 14-16: A/D Conversion Timing
- TABLE 14-10: A/D Conversion Requirements
- 15.0 DC and AC Characteristics Graphs and Tables
- FIGURE 15-1: Typical Idd vs. Fosc OVER Vdd (HS Mode)
- FIGURE 15-2: Maximum Idd vs. Fosc OVER Vdd (HS Mode)
- FIGURE 15-3: Typical Idd vs. Fosc OVER Vdd (XT Mode)
- FIGURE 15-4: Maximum Idd vs. Fosc OVER Vdd (XT Mode)
- FIGURE 15-5: Typical Idd vs. Fosc OVER Vdd (LP Mode)
- FIGURE 15-6: Maximum Idd vs. Fosc OVER Vdd (LP Mode)
- FIGURE 15-7: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20pF, 25°C)
- FIGURE 15-8: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, 25°C)
- FIGURE 15-9: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, 25°C)
- FIGURE 15-10: Ipd vs. Vdd (Sleep Mode, all peripherals disabled)
- FIGURE 15-11: DIbor vs. Vdd over Temperature
- FIGURE 15-12: TYPICAL AND MAXIMUM DItmr1 vs. Vdd over Temperature (-10°C TO +70°C, Timer1 with Os...
- FIGURE 15-13: TYPICAL AND MAXIMUM DIwdt vs. Vdd over Temperature
- FIGURE 15-14: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to +125°C)
- FIGURE 15-15: Average WDT Period vs. Vdd over Temperature (-40°C to +125°C)
- FIGURE 15-16: Typical, Minimum and Maximum Voh vs. Ioh (Vdd=5V, -40°C to +125°C)
- FIGURE 15-17: Typical, Minimum and Maximum Voh vs. Ioh (Vdd=3V, -40°C to +125°C)
- FIGURE 15-18: Typical, Minimum and Maximum Vol vs. Iol (Vdd=5V, -40°C to 125°C)
- FIGURE 15-19: Typical, Minimum and Maximum Vol vs. Iol (Vdd=3V, -40°C to +125°C)
- FIGURE 15-20: Minimum and Maximum Vin vs. Vdd, (TTL Input, -40°C to +125°C)
- FIGURE 15-21: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C)
- FIGURE 15-22: Minimum and Maximum Vin vs. Vdd (I2C Input, -40°C to +125°C)
- 16.0 Packaging Information
- Appendix A: Revision History
- Appendix B: Conversion Considerations
- Index
- A
- A/D 79
- Absolute Maximum Ratings 117
- ACK pulse 59
- ACKDT Bit
- ACKEN Bit
- Acknowledge Pulse (ACK) 59
- ACKSTAT Bit
- ACKSTAT Status Flag 67
- ADCON0 Register 9
- ADCON1 Register 10
- ADRESH Register 9
- ADRESL Register 10
- Analog-to-Digital Converter. See A/D
- Application Notes
- Assembler
- Banking, Data Memory 7
- BCLIF Bit 18
- BF Bit
- BF Status Flag 67, 69
- Block Diagrams
- BOR. See Brown-out Reset
- Brown-out Reset (BOR) 87, 91, 92, 93
- Bus Arbitration 73
- Bus Collision
- Bus Collision During a Repeated START Condition 76
- Bus Collision During a START Condition 74
- Bus Collision During a STOP Condition 77
- Bus Collision Interrupt Flag (BCLIF) 18
- Capture Mode
- Capture/Compare/PWM (CCP) 45
- CCP. See Capture/Compare/PWM
- CCP1CON Register 9
- CCP1M3:CCP1M0 bits 45
- CCP1X bit 45
- CCP1Y bit 45
- CCPR1H Register 9, 45
- CCPR1L Register 9, 45
- CKE Bit 52
- CKP Bit 53
- Clock Polarity Select Bit (CKP) 53
- Code Examples
- Code Protected Operation
- Code Protection 87, 101
- Compare Mode
- Computed GOTO 20
- Configuration Bits 87
- Configuration Word 88
- Conversion Considerations 155
- D/A Bit 52
- Data EEPROM 23
- Data Memory 7
- Data/Address Bit (D/A) 52
- DC and AC Characteristics Graphs and Tables 139
- DC Characteristics
- Development Support 111
- Device Overview 3
- Direct Addressing 21
- EECON1 and EECON2 Registers 23
- EECON1 Register 11
- EECON2 Register 11
- Electrical Characteristics 117
- Equations
- Errata 2
- External Clock Timing Requirements 127
- Firmware Instructions 103
- FLASH Program Memory 23
- FSR Register 9, 21
- GCEN Bit
- General Call Address Support 61
- I/O Ports 29
- I2C Bus
- I2C Mode
- ICEPIC In-Circuit Emulator 112
- ID Locations 87, 101
- In-Circuit Debugger 87, 101
- In-Circuit Serial Programming (ICSP) 87, 102
- INDF Register 9
- Indirect Addressing 21
- Instruction Format 103
- Instruction Set 103
- INT Interrupt (RB0/INT). See Interrupt Sources
- INTCON Register 9, 14
- Inter-Integrated Circuit (I2C) 51
- Internal Sampling Switch (Rss) Impedance 82
- Interrupt Sources 87, 97
- Interrupts
- Interrupts, Context Saving During 98
- Interrupts, Enable Bits
- Interrupts, Flag Bits
- KeeLoq Evaluation and Programming Tools 114
- Load Conditions 126
- Loading of PC 20
- Low Voltage ICSP Programming 102
- Low Voltage In-Circuit Serial Programming 87
- Master Clear (MCLR)
- Master Synchronous Serial Port. See MSSP
- MCLR/Vpp Pin 5
- Memory Organization 7
- MPLAB C17 and MPLAB C18 C Compilers 111
- MPLAB ICD In-Circuit Debugger 113
- MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE 112
- MPLAB Integrated Development Environment Software 111
- MPLINK Object Linker/MPLIB Object Librarian 112
- MSSP 51
- Multi-Master Communication 73
- OPCODE Field Descriptions 103
- OPTION_REG Register 10, 13
- OSC1/CLKI Pin 5
- OSC2/CLKO Pin 5
- Oscillator Configuration
- Oscillator Selection 87
- Oscillator, WDT 99
- Oscillators
- P Bit
- Packaging 151– 154
- PCL Register 9, 10, 20
- PCLATH Register 9, 20
- PCON Register 10, 19, 92
- PEN Bit
- PICDEM 1 Low Cost PICmicro Demonstration Board 113
- PICDEM 17 Demonstration Board 114
- PICDEM 2 Low Cost PIC16CXX Demonstration Board 113
- PICDEM 3 Low Cost PIC16CXXX Demonstration Board 114
- PICSTART Plus Entry Level Development Programmer 113
- PIE1 Register 10, 15
- PIE2 Register 10, 17
- Pinout Descriptions 5– 6
- PIR1 Register 9, 16
- PIR2 Register 9, 18
- POP 20
- POR. See Power-on Reset
- PORTA 5
- PORTB 6
- PORTC 6
- Power-down Mode. See SLEEP
- Power-on Reset (POR) 87, 91, 92, 93
- PR2 Register 10, 43
- PRO MATE II Universal Device Programmer 113
- Program Counter
- Program Memory
- Program Verification 101
- Programming, Device Instructions 103
- Pulse Width Modulation.See Capture/Compare/PWM, PWM Mode.
- PUSH 20
- PWM Mode
- R/W Bit 59
- R/W Bit 59
- RA0/AN0 Pin 5
- RA1/AN1 Pin 5
- RA2/AN2/Vref- Pin 5
- RA3/AN3/Vref+ Pin 5
- RA4/T0CKI Pin 5
- RA5/SS/AN4 Pin 5
- RAM. See Data Memory
- RB0/INT Pin 6
- RB1 Pin 6
- RB2 Pin 6
- RB3/PGM Pin 6
- RB4 Pin 6
- RB5 Pin 6
- RB6/PGC Pin 6
- RB7/PGD Pin 6
- RC0/T1OSO/T1CKI Pin 6
- RC1/T1OSI Pin 6
- RC2/CCP1 Pin 6
- RC3/SCK/SCL Pin 6
- RC4/SDI/SDA Pin 6
- RC5/SDO Pin 6
- RC6 Pin 6
- RC7 Pin 6
- RCEN Bit
- Receive Overflow Indicator Bit (SSPOV) 53
- Registers
- RESET 87, 91
- RESET
- Revision History 155
- RSEN Bit
- S Bit
- Sample Bit (SMP) 52
- SCK Pin 55
- SCL Pin 58
- SDA Pin 58
- SDI Pin 55
- SDO Pin 55
- SEN Bit
- Serial Clock (SCK) 55
- Serial Clock (SCL) 58
- Serial Data Address (SDA) 58
- Serial Data In (SDI) 55
- Serial Data Out (SDO) 55
- Slave Select (SS) 55
- SLEEP 87, 91, 100
- SMP Bit 52
- Software Simulator (MPLAB SIM) 112
- Special Features of the CPU 87
- Special Function Registers (SFRs) 9
- Speed, Operating 1
- SPI Clock Edge Select Bit (CKE) 52
- SPI Mode
- SS Pin 55
- SSBUF Register 9
- MSSP
- SSPADD Register 10
- SSPBUF register 58
- SSPCON Register 9
- SSPCON2 Register 10
- SSPEN Bit 53
- SSPIF 16, 59
- SSPM3:SSPM0 Bits 53
- SSPOV Bit 53, 59
- SSPOV Status Flag 69
- SSPSTAT Register 10, 58
- Stack 20
- STATUS Register 9, 12
- Synchronous Serial Port Enable Bit (SSPEN) 53
- Synchronous Serial Port Interrupt 16
- Synchronous Serial Port Mode Select Bits (SSPM3:SSPM0) 53
- T1CKPS0 bit 39
- T1CKPS1 bit 39
- T1CON Register 9
- T1OSCEN bit 39
- T1SYNC bit 39
- T2CON Register 9
- Time-out Sequence 92
- Timer0 35
- Timer1 39
- Timer2 43
- Timing Diagrams
- Timing Parameter Symbology 126
- TMR0 Register 9, 11
- TMR1CS bit 39
- TMR1H Register 9
- TMR1L Register 9
- TMR1ON bit 39
- TMR2 Register 9
- TOUTPS3:TOUTPS0 bits 43
- TRISA Register 10
- TRISB Register 10
- TRISC Register 10
- UA Bit
- Wake-up from SLEEP 87, 100
- Wake-Up Using Interrupts 100
- Watchdog Timer (WDT) 87, 99
- WCOL 65
- WCOL Bit 53
- WCOL Status Flag 65, 67, 69, 71
- Write Collision Detect Bit (WCOL) 53
- Write Verify
- WWW, On-Line Support 2
- On-Line Support
- Reader Response
- PIC16F872 Product Identification System
- Worldwide Sales and Service
PIC16F872
DS30221B-page 62 2002 Microchip Technology Inc.
9.2.3 SLEEP OPERATION
While in SLEEP mode, the I
2
C module can receive
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
9.2.4 EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
TABLE 9-3: REGISTERS ASSOCIATED WITH I
2
C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh
INTCON GIE PEIE
TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
0Dh PIR2 — (1) — EEIF BCLIF — (1) CCP2IF -r-0 0--0 -r-0 0--0
8Dh PIE2 — (1) — EEIE BCLIE — (1) CCP2IE -r-0 0--r -r-0 0--r
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I
2
C mode.
Note 1: These bits are reserved; always maintain these bits clear.