Datasheet

 2002 Microchip Technology Inc. DS30221B-page 53
PIC16F872
REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS: 14h)
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
Master mode:
1 = A write to SSPBUF was attempted while the I
2
C conditions were not valid
0 = No collision
Slave mode:
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow.
In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid over-
flows. In Master mode, the overflow bit is not set since each operation is initiated by writing to
the SSPBUF register. (Must be cleared in software.)
0 = No overflow
In I
2
C mode:
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in
Transmit mode. (Must be cleared in software.)
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In SPI mode
:
When enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS
as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
2
C mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
In I
2
C slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
2
C master mode:
Unused in this mode
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
OSC/4
0001 = SPI Master mode, clock = F
OSC/16
0010 = SPI Master mode, clock = F
OSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS
pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS
pin control disabled. SS can be used as I/O pin.
0110 =I
2
C Slave mode, 7-bit address
0111 =I
2
C Slave mode, 10-bit address
1000 =I
2
C Master mode, clock = FOSC / (4 * (SSPADD+1)
1011 =I
2
C Firmware Controlled Master mode (slave idle)
1110 =I
2
C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts
enabled
1111 =I
2
C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts
enabled
1001, 1010, 1100, 1101 = reserved
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown