Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 28 8-Bit 20 MHz I/O number 22

Table Of Contents

High Performance RISC CPU:
Peripheral Features:
CMOS Technology:
Pin Diagram
Special Microcontroller Features:
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- TABLE 1-1: Key Features of the PIC16F872
- FIGURE 1-1: PIC16F872 Block Diagram
- TABLE 1-2: PIC16F872 Pinout Description
2.0 Memory Organization
- 2.1 Program Memory Organization
  - FIGURE 2-1: PIC16F872 Program Memory Map and Stack
- 2.2 Data Memory Organization
  - 2.2.1 General purpose Register File
    - FIGURE 2-2: PIC16F872 Register File Map
  - 2.2.2 Special Function Registers
- 2.3 PCL and PCLATH
- 2.4 Program Memory Paging
- 2.5 Indirect Addressing, INDF and FSR Registers
  - EXAMPLE 2-1: Indirect Addressing
  - FIGURE 2-4: Direct/Indirect Addressing
3.0 Data EEPROM and Flash Program Memory
- 3.1 EECON1 and EECON2 Registers
  - Register 3-1: EECON1 Register (Address 18Ch)
- 3.2 Reading the EEPROM Data Memory
  - EXAMPLE 3-1: EEPROM DATA READ
- 3.3 Writing to the EEPROM Data Memory
  - EXAMPLE 3-2: EEPROM DATA WRITE
- 3.4 Reading the FLASH Program Memory
  - EXAMPLE 3-3: FLASH PROGRAM READ
- 3.5 Writing to the FLASH Program Memory
  - EXAMPLE 3-4: FLASH PROGRAM WRITE
- 3.6 Write Verify
- 3.7 Protection Against Spurious Writes
- 3.8 Operation While Code Protected
- 3.9 FLASH Program Memory Write Protection
  - TABLE 3-1: Read/Write State of Internal FLASH Program memory
  - TABLE 3-2: Registers Associated with DATA EEPROM/PROGRAM FLASH
4.0 I/O Ports
- 4.1 PORTA and the TRISA Register
- 4.2 PORTB and the TRISB Register
- 4.3 PORTC and the TRISC Register
5.0 Timer0 Module
- 5.1 Timer0 Interrupt
  - FIGURE 5-1: Block Diagram of the Timer0/WDT Prescaler
- 5.2 Using Timer0 with an External Clock
- 5.3 Prescaler
  - Register 5-1: OPTION_REG Register
  - TABLE 5-1: Registers Associated with Timer0
6.0 Timer1 Module
- Register 6-1: T1CON: Timer1 Control Register (Address 10h)
- 6.1 Timer1 Operation in Timer Mode
- 6.2 Timer1 Counter Operation
  - FIGURE 6-1: Timer1 Incrementing Edge
- 6.3 Timer1 Operation in Synchronized Counter Mode
  - FIGURE 6-2: Timer1 Block Diagram
- 6.4 Timer1 Operation in Asynchronous Counter Mode
  - 6.4.1 Reading and writing Timer1 in asynchronous counter mode
- 6.5 Timer1 Oscillator
  - TABLE 6-1: Capacitor Selection for the Timer1 Oscillator
- 6.6 Resetting Timer1 using a CCP Trigger Output
- 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L)
- 6.8 Timer1 Prescaler
  - TABLE 6-2: Registers Associated with Timer1 as a Timer/Counter
7.0 Timer2 Module
- FIGURE 7-1: Timer2 Block Diagram
- Register 7-1: T2CON: Timer2 Control Register (Address 12h)
- 7.1 Timer2 Prescaler and Postscaler
- 7.2 Output of TMR2
  - TABLE 7-1: Registers Associated with Timer2 as a Timer/Counter
8.0 Capture/Compare/PWM Module
- TABLE 8-1: CCP Mode - Timer ResourceS REQUIRED
- Register 8-1: CCP1CON Register (Address: 17h)
- 8.1 Capture Mode
- 8.2 Compare Mode
- 8.3 PWM Mode (PWM)
9.0 Master Synchronous Serial Port (MSSP) Module
- Register 9-1: SSPSTAT: Sync Serial Port Status Register (Address: 94h)
- Register 9-2: SSPCON: Sync Serial Port Control Register (Address: 14h)
- Register 9-3: SSPCON2: Sync Serial Port Control Register2 (Address: 91h)
- 9.1 SPI Mode
- 9.2 MSSP I2C Operation
- 9.3 Connection Considerations for I2C Bus
  - FIGURE 9-27: Sample device configuration for I2C bus
10.0 Analog-to-Digital Converter (A/D) Module
- Register 10-1: ADCON0 Register (Address: 1Fh)
- Register 10-2: ADCON1 Register (Address: 9Fh)
- FIGURE 10-1: A/D Block Diagram
- 10.1 A/D Acquisition Requirements
  - EQUATION 10-1: Acquisition Time
  - FIGURE 10-2: Analog Input Model
- 10.2 Selecting the A/D Conversion Clock
- 10.3 Configuring Analog Port Pins
  - TABLE 10-1: Tad vs. Maximum Device Operating Frequencies (Standard devices (C))
- 10.4 A/D Conversions
  - FIGURE 10-3: A/D Conversion Tad Cycles
  - 10.4.1 A/D Result Registers
    - FIGURE 10-4: A/D Result Justification
- 10.5 A/D Operation During SLEEP
- 10.6 Effects of a RESET
  - TABLE 10-2: Registers/bits Associated with A/D
11.0 Special Features of the CPU
- 11.1 Configuration Bits
  - Register 11-1: Configuration Word (ADDRESS: 2007H)(1)
- 11.2 Oscillator Configurations
- 11.3 Reset
  - FIGURE 11-4: Simplified Block Diagram of On-chip Reset Circuit
- 11.4 Power-on Reset (POR)
- 11.5 Power-up Timer (PWRT)
- 11.6 Oscillator Start-up Timer (OST)
- 11.7 Brown-out Reset (BOR)
- 11.8 Time-out Sequence
- 11.9 Power Control/Status Register (PCON)
- 11.10 Interrupts
- 11.11 Context Saving During Interrupts
  - EXAMPLE 11-1: Saving STATUS, W, and PCLATH Registers in RAM
- 11.12 Watchdog Timer (WDT)
  - FIGURE 11-10: Watchdog Timer Block Diagram
  - TABLE 11-7: Summary of Watchdog Timer Registers
- 11.13 Power-down Mode (SLEEP)
  - 11.13.1 Wake-up from SLEEP
  - 11.13.2 Wake-Up Using Interrupts
    - FIGURE 11-11: Wake-up from Sleep Through Interrupt
- 11.14 In-Circuit Debugger
  - TABLE 11-8: Debugger Resources
- 11.15 Program Verification/Code Protection
- 11.16 ID Locations
- 11.17 In-Circuit Serial Programming
- 11.18 Low Voltage ICSP Programming
12.0 Instruction Set Summary
- 12.1 READMODIFY-WRITE OPERATIONS
- 12.2 Instruction Descriptions
13.0 Development Support
- 13.1 MPLAB Integrated Development Environment Software
- 13.2 MPASM Assembler
- 13.3 MPLAB C17 and MPLAB C18 C Compilers
- 13.4 MPLINK Object Linker/ MPLIB Object Librarian
- 13.5 MPLAB SIM Software Simulator
- 13.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
- 13.7 ICEPIC In-Circuit Emulator
- 13.8 MPLAB ICD In-Circuit Debugger
- 13.9 PRO MATE II Universal Device Programmer
- 13.10 PICSTART Plus Entry Level Development Programmer
- 13.11 PICDEM 1 Low Cost PICmicro Demonstration Board
- 13.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
- 13.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
- 13.14 PICDEM 17 Demonstration Board
- 13.15 KeeLoq Evaluation and Programming Tools
  - TABLE 13-1: DEVELOPMENT TOOLS FROM MICROCHIP
14.0 Electrical Characteristics
- FIGURE 14-1: PIC16F872 Voltage-Frequency Graph
- FIGURE 14-2: PIC16LF872 Voltage-Frequency Graph
- 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial)
- 14.2 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial)
- 14.3 DC Characteristics: PIC16F872 (Extended)
- 14.4 DC Characteristics: PIC16F872 (Extended)
- 14.5 Timing Parameter Symbology
15.0 DC and AC Characteristics Graphs and Tables
- FIGURE 15-1: Typical Idd vs. Fosc OVER Vdd (HS Mode)
- FIGURE 15-2: Maximum Idd vs. Fosc OVER Vdd (HS Mode)
- FIGURE 15-3: Typical Idd vs. Fosc OVER Vdd (XT Mode)
- FIGURE 15-4: Maximum Idd vs. Fosc OVER Vdd (XT Mode)
- FIGURE 15-5: Typical Idd vs. Fosc OVER Vdd (LP Mode)
- FIGURE 15-6: Maximum Idd vs. Fosc OVER Vdd (LP Mode)
- FIGURE 15-7: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20pF, 25°C)
- FIGURE 15-8: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, 25°C)
- FIGURE 15-9: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, 25°C)
- FIGURE 15-10: Ipd vs. Vdd (Sleep Mode, all peripherals disabled)
- FIGURE 15-11: DIbor vs. Vdd over Temperature
- FIGURE 15-12: TYPICAL AND MAXIMUM DItmr1 vs. Vdd over Temperature (-10°C TO +70°C, Timer1 with Os...
- FIGURE 15-13: TYPICAL AND MAXIMUM DIwdt vs. Vdd over Temperature
- FIGURE 15-14: Typical, Minimum and Maximum WDT Period vs. Vdd (-40°C to +125°C)
- FIGURE 15-15: Average WDT Period vs. Vdd over Temperature (-40°C to +125°C)
- FIGURE 15-16: Typical, Minimum and Maximum Voh vs. Ioh (Vdd=5V, -40°C to +125°C)
- FIGURE 15-17: Typical, Minimum and Maximum Voh vs. Ioh (Vdd=3V, -40°C to +125°C)
- FIGURE 15-18: Typical, Minimum and Maximum Vol vs. Iol (Vdd=5V, -40°C to 125°C)
- FIGURE 15-19: Typical, Minimum and Maximum Vol vs. Iol (Vdd=3V, -40°C to +125°C)
- FIGURE 15-20: Minimum and Maximum Vin vs. Vdd, (TTL Input, -40°C to +125°C)
- FIGURE 15-21: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C)
- FIGURE 15-22: Minimum and Maximum Vin vs. Vdd (I2C Input, -40°C to +125°C)
16.0 Packaging Information
- 16.1 Package Marking Information
Appendix A: Revision History
Appendix B: Conversion Considerations
- TABLE B-1: Conversion Considerations
Index
- A
- A/D 79
- Absolute Maximum Ratings 117
- ACK pulse 59
- ACKDT Bit
- ACKEN Bit
- Acknowledge Pulse (ACK) 59
- ACKSTAT Bit
- ACKSTAT Status Flag 67
- ADCON0 Register 9
- ADCON1 Register 10
- ADRESH Register 9
- ADRESL Register 10
- Analog-to-Digital Converter. See A/D
- Application Notes
- Assembler
  - B
- Banking, Data Memory 7
- BCLIF Bit 18
- BF Bit
- BF Status Flag 67, 69
- Block Diagrams
- BOR. See Brown-out Reset
- Brown-out Reset (BOR) 87, 91, 92, 93
- Bus Arbitration 73
- Bus Collision
- Bus Collision During a Repeated START Condition 76
- Bus Collision During a START Condition 74
- Bus Collision During a STOP Condition 77
- Bus Collision Interrupt Flag (BCLIF) 18
  - C
- Capture Mode
- Capture/Compare/PWM (CCP) 45
- CCP. See Capture/Compare/PWM
- CCP1CON Register 9
- CCP1M3:CCP1M0 bits 45
- CCP1X bit 45
- CCP1Y bit 45
- CCPR1H Register 9, 45
- CCPR1L Register 9, 45
- CKE Bit 52
- CKP Bit 53
- Clock Polarity Select Bit (CKP) 53
- Code Examples
- Code Protected Operation
- Code Protection 87, 101
- Compare Mode
- Computed GOTO 20
- Configuration Bits 87
- Configuration Word 88
- Conversion Considerations 155
  - D
- D/A Bit 52
- Data EEPROM 23
- Data Memory 7
- Data/Address Bit (D/A) 52
- DC and AC Characteristics Graphs and Tables 139
- DC Characteristics
- Development Support 111
- Device Overview 3
- Direct Addressing 21
  - E
- EECON1 and EECON2 Registers 23
- EECON1 Register 11
- EECON2 Register 11
- Electrical Characteristics 117
- Equations
- Errata 2
- External Clock Timing Requirements 127
  - F
- Firmware Instructions 103
- FLASH Program Memory 23
- FSR Register 9, 21
  - G
- GCEN Bit
- General Call Address Support 61
  - I
- I/O Ports 29
- I2C Bus
- I2C Mode
- ICEPIC In-Circuit Emulator 112
- ID Locations 87, 101
- In-Circuit Debugger 87, 101
- In-Circuit Serial Programming (ICSP) 87, 102
- INDF Register 9
- Indirect Addressing 21
- Instruction Format 103
- Instruction Set 103
- INT Interrupt (RB0/INT). See Interrupt Sources
- INTCON Register 9, 14
- Inter-Integrated Circuit (I2C) 51
- Internal Sampling Switch (Rss) Impedance 82
- Interrupt Sources 87, 97
- Interrupts
- Interrupts, Context Saving During 98
- Interrupts, Enable Bits
- Interrupts, Flag Bits
  - K
- KeeLoq Evaluation and Programming Tools 114
  - L
- Load Conditions 126
- Loading of PC 20
- Low Voltage ICSP Programming 102
- Low Voltage In-Circuit Serial Programming 87
  - M
- Master Clear (MCLR)
- Master Synchronous Serial Port. See MSSP
- MCLR/Vpp Pin 5
- Memory Organization 7
- MPLAB C17 and MPLAB C18 C Compilers 111
- MPLAB ICD In-Circuit Debugger 113
- MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE 112
- MPLAB Integrated Development Environment Software 111
- MPLINK Object Linker/MPLIB Object Librarian 112
- MSSP 51
- Multi-Master Communication 73
  - O
- OPCODE Field Descriptions 103
- OPTION_REG Register 10, 13
- OSC1/CLKI Pin 5
- OSC2/CLKO Pin 5
- Oscillator Configuration
- Oscillator Selection 87
- Oscillator, WDT 99
- Oscillators
  - P
- P Bit
- Packaging 151– 154
- PCL Register 9, 10, 20
- PCLATH Register 9, 20
- PCON Register 10, 19, 92
- PEN Bit
- PICDEM 1 Low Cost PICmicro Demonstration Board 113
- PICDEM 17 Demonstration Board 114
- PICDEM 2 Low Cost PIC16CXX Demonstration Board 113
- PICDEM 3 Low Cost PIC16CXXX Demonstration Board 114
- PICSTART Plus Entry Level Development Programmer 113
- PIE1 Register 10, 15
- PIE2 Register 10, 17
- Pinout Descriptions 5– 6
- PIR1 Register 9, 16
- PIR2 Register 9, 18
- POP 20
- POR. See Power-on Reset
- PORTA 5
- PORTB 6
- PORTC 6
- Power-down Mode. See SLEEP
- Power-on Reset (POR) 87, 91, 92, 93
- PR2 Register 10, 43
- PRO MATE II Universal Device Programmer 113
- Program Counter
- Program Memory
- Program Verification 101
- Programming, Device Instructions 103
- Pulse Width Modulation.See Capture/Compare/PWM, PWM Mode.
- PUSH 20
- PWM Mode
  - R
- R/W Bit 59
- R/W Bit 59
- RA0/AN0 Pin 5
- RA1/AN1 Pin 5
- RA2/AN2/Vref- Pin 5
- RA3/AN3/Vref+ Pin 5
- RA4/T0CKI Pin 5
- RA5/SS/AN4 Pin 5
- RAM. See Data Memory
- RB0/INT Pin 6
- RB1 Pin 6
- RB2 Pin 6
- RB3/PGM Pin 6
- RB4 Pin 6
- RB5 Pin 6
- RB6/PGC Pin 6
- RB7/PGD Pin 6
- RC0/T1OSO/T1CKI Pin 6
- RC1/T1OSI Pin 6
- RC2/CCP1 Pin 6
- RC3/SCK/SCL Pin 6
- RC4/SDI/SDA Pin 6
- RC5/SDO Pin 6
- RC6 Pin 6
- RC7 Pin 6
- RCEN Bit
- Receive Overflow Indicator Bit (SSPOV) 53
- Registers
- RESET 87, 91
- RESET
- Revision History 155
- RSEN Bit
  - S
- S Bit
- Sample Bit (SMP) 52
- SCK Pin 55
- SCL Pin 58
- SDA Pin 58
- SDI Pin 55
- SDO Pin 55
- SEN Bit
- Serial Clock (SCK) 55
- Serial Clock (SCL) 58
- Serial Data Address (SDA) 58
- Serial Data In (SDI) 55
- Serial Data Out (SDO) 55
- Slave Select (SS) 55
- SLEEP 87, 91, 100
- SMP Bit 52
- Software Simulator (MPLAB SIM) 112
- Special Features of the CPU 87
- Special Function Registers (SFRs) 9
- Speed, Operating 1
- SPI Clock Edge Select Bit (CKE) 52
- SPI Mode
- SS Pin 55
- SSBUF Register 9
- MSSP
- SSPADD Register 10
- SSPBUF register 58
- SSPCON Register 9
- SSPCON2 Register 10
- SSPEN Bit 53
- SSPIF 16, 59
- SSPM3:SSPM0 Bits 53
- SSPOV Bit 53, 59
- SSPOV Status Flag 69
- SSPSTAT Register 10, 58
- Stack 20
- STATUS Register 9, 12
- Synchronous Serial Port Enable Bit (SSPEN) 53
- Synchronous Serial Port Interrupt 16
- Synchronous Serial Port Mode Select Bits (SSPM3:SSPM0) 53
  - T
- T1CKPS0 bit 39
- T1CKPS1 bit 39
- T1CON Register 9
- T1OSCEN bit 39
- T1SYNC bit 39
- T2CON Register 9
- Time-out Sequence 92
- Timer0 35
- Timer1 39
- Timer2 43
- Timing Diagrams
- Timing Parameter Symbology 126
- TMR0 Register 9, 11
- TMR1CS bit 39
- TMR1H Register 9
- TMR1L Register 9
- TMR1ON bit 39
- TMR2 Register 9
- TOUTPS3:TOUTPS0 bits 43
- TRISA Register 10
- TRISB Register 10
- TRISC Register 10
  - U
- UA Bit
  - W
- Wake-up from SLEEP 87, 100
- Wake-Up Using Interrupts 100
- Watchdog Timer (WDT) 87, 99
- WCOL 65
- WCOL Bit 53
- WCOL Status Flag 65, 67, 69, 71
- Write Collision Detect Bit (WCOL) 53
- Write Verify
- WWW, On-Line Support 2
On-Line Support
- Connecting to the Microchip Internet Web Site
- Systems Information and Upgrade Hot Line
Reader Response
PIC16F872 Product Identification System
Worldwide Sales and Service

PIC16F872

DS30221B-page 10  2002 Microchip Technology Inc.

Bank 1

80h

(2)

INDF Addressing this location uses contents of FSR to address data memory

(not a physical register)

0000 0000 21, 93

81h OPTION_REG RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13, 94

82h

(2)

PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93

83h

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 12, 93

84h

(2)

FSR Indirect data memory address pointer xxxx xxxx 21, 93

85h TRISA

— — PORTA Data Direction Register --11 1111 29, 94

86h TRISB PORTB Data Direction Register

1111 1111 31, 94

87h TRISC PORTC Data Direction Register

1111 1111 33, 94

88h — Unimplemented — —

89h — Unimplemented — —

8Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93

8Bh

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93

8Ch PIE1 (3) ADIE (3) (3) SSPIE CCP1IE TMR2IE TMR1IE

r0rr 0000 15, 94

8Dh PIE2

— (3) — EEIE BCLIE — — (3) -r-0 0--r 17, 94

8Eh PCON

— — — — — — POR BOR ---- --qq 19, 94

8Fh — Unimplemented — —

90h — Unimplemented — —

91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

0000 0000 54, 94

92h PR2 Timer2 Period Register

1111 1111 43, 94

93h SSPADD Synchronous Serial Port (I

C mode) Address Register 0000 0000 58, 94

94h SSPSTAT SMP CKE D/A

PSR/WUA BF 0000 0000 52, 94

95h — Unimplemented — —

96h — Unimplemented — —

97h — Unimplemented — —

95h — Unimplemented — —

9Ah — Unimplemented — —

9Bh — Unimplemented — —

9Ch — Unimplemented — —

9Dh — Unimplemented — —

9Eh ADRESL A/D Result Register Low Byte

xxxx xxxx 84, 94

9Fh ADCON1 ADFM

— — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 80, 94

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Details

page:

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.

3: These bits are reserved; always maintain these bits clear.