Datasheet

 2000-2013 Microchip Technology Inc. DS30569C-page 97
PIC16F870/871
FIGURE 11-9: INTERRUPT LOGIC
11.10.1 INT INTERRUPT
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.13 for details on SLEEP
mode.
11.10.2 TMR0 INTERRUPT
An overflow (FFh  00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 5.0).
11.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 4.2).
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
The following table shows which devices have which interrupts.
Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF EEIF
PIC18F870 Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes
PIC18F871 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
EEIF
EEIE