Datasheet

 2000-2013 Microchip Technology Inc. DS30569C-page 165
PIC16F870/871
STATUS Register .........................................................13, 15
PD
Bit.......................................................................... 91
TO
Bit.......................................................................... 91
Synchronous Master Reception
Associated Registers .................................................. 75
Synchronous Master Transmission
Associated Registers .................................................. 73
Synchronous Slave Reception
Associated Registers .................................................. 77
Synchronous Slave Transmission
Associated Registers .................................................. 76
T
T1CKPS0 Bit....................................................................... 49
T1CKPS1 Bit....................................................................... 49
T1CON Register ................................................................. 13
T1OSCEN Bit...................................................................... 49
T1SYNC
Bit......................................................................... 49
T2CKPS0 Bit....................................................................... 53
T2CKPS1 Bit....................................................................... 53
T2CON Register ................................................................. 13
T
AD......................................................................................83
Time-out Sequence.............................................................92
Timer0.................................................................................45
Associated Registers .................................................. 47
Clock Source Edge Select (T0SE Bit)......................... 17
Clock Source Select (T0CS Bit).................................. 17
External Clock.............................................................46
Interrupt....................................................................... 45
Overflow Enable (T0IE Bit) ......................................... 18
Overflow Flag (T0IF Bit).............................................. 97
Overflow Interrupt .......................................................97
Prescaler.....................................................................46
T0CKI.......................................................................... 46
Timer1.................................................................................49
Associated Registers .................................................. 52
Asynchronous Counter Mode
Reading and Writing to ....................................... 51
Counter Operation ...................................................... 50
Incrementing Edge (figure) ......................................... 50
Operation in Asynchronous Counter Mode.................51
Operation in Synchronized Counter Mode.................. 50
Operation in Timer Mode ............................................50
Oscillator.....................................................................51
Capacitor Selection............................................. 51
Prescaler.....................................................................52
Resetting of Timer1 Register Pair
(TMR1H, TMR1L) ...............................................52
Resetting Timer1 Using a CCP Trigger Output........... 51
TMR1H........................................................................ 51
TMR1L ........................................................................51
Timer2.................................................................................53
Associated Registers .................................................. 54
Output .........................................................................54
Postscaler ................................................................... 53
Prescaler.....................................................................53
Prescaler and Postscaler............................................ 54
Timing Diagrams
A/D Conversion.........................................................135
Asynchronous Master Transmission........................... 67
Asynchronous Master Transmission
(Back to Back) ....................................................67
Asynchronous Reception with
Address Byte First .............................................. 71
Asynchronous Reception with
Address Detect................................................... 71
Brown-out Reset....................................................... 129
Capture/Compare/PWM (CCP1) .............................. 131
CLKO and I/O........................................................... 128
External Clock .......................................................... 126
Parallel Slave Port (PSP) Read.................................. 43
Parallel Slave Port (PSP) Write .................................. 43
RESET, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer................. 129
Slow Rise Time (MCLR
Tied to VDD) ......................... 96
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD)
Case 1 ................................................................ 95
Case 2 ................................................................ 95
Time-out Sequence on Power-up
(MCLR
Tied to VDD) ........................................... 95
Timer0 and Timer1 External Clock ........................... 130
USART Asynchronous Reception .............................. 68
USART Synchronous Receive (Master/Slave) ......... 133
USART Synchronous Reception
(Master Mode, SREN) ........................................ 75
USART Synchronous Transmission........................... 73
USART Synchronous Transmission
(Master/Slave).................................................. 133
Wake-up from SLEEP via Interrupt .......................... 101
Timing Parameter Symbology .......................................... 125
TMR0 Register.............................................................. 13, 15
TMR1CS Bit........................................................................ 49
TMR1H Register................................................................. 13
TMR1L Register.................................................................. 13
TMR1ON Bit ....................................................................... 49
TMR2 Register.................................................................... 13
TMR2ON Bit ....................................................................... 53
TOUTPS0 Bit...................................................................... 53
TOUTPS1 Bit...................................................................... 53
TOUTPS2 Bit...................................................................... 53
TOUTPS3 Bit...................................................................... 53
TRISA ................................................................................. 15
TRISA Register................................................................... 14
TRISB ................................................................................. 15
TRISB Register............................................................. 14, 15
TRISC................................................................................. 15
TRISC Register................................................................... 14
TRISD................................................................................. 15
TRISD Register................................................................... 14
TRISE ................................................................................. 15
TRISE Register................................................................... 14
IBF Bit......................................................................... 40
IBOV Bit...................................................................... 40
OBF Bit....................................................................... 40
PSPMODE Bit .......................................... 38, 39, 40, 42
TXREG Register................................................................. 13
TXSTA................................................................................ 15
TXSTA Register.................................................................. 14
BRGH Bit.................................................................... 61
CSRC Bit .................................................................... 61
TRMT Bit .................................................................... 61
TX9 Bit........................................................................ 61
TX9D Bit ..................................................................... 61
TXEN Bit..................................................................... 61