Datasheet

 2000-2013 Microchip Technology Inc. DS30569C-page 135
PIC16F870/871
FIGURE 14-13: A/D CONVERSION TIMING
TABLE 14-10: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(T
OSC/2)
(1)
987 210
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY


Param
No.
Sym Characteristic Min Typ† Max Units Conditions
130 T
AD A/D clock period
Standard(F)
1.6 — — sTOSC based, VREF  3.0V
Extended(LF)3.0——sT
OSC based, VREF  2.0V
Standard(F) 2.0 4.0 6.0 s A/D RC Mode
Extended(LF) 3.0 6.0 9.0 s A/D RC Mode
131 T
CNV Conversion time (not including S/H time)
(Note 1)
—12TAD
132 TACQ Acquisition time (Note 2)
10*
40
—
—
—
s
s The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than
1 LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on C
HOLD).
134 T
GO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is
selected as RC, a time of T
CY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 10.1 for min conditions.