Datasheet

 2000-2013 Microchip Technology Inc. DS30569C-page 11
PIC16F870/871
2.0 MEMORY ORGANIZATION
The PIC16F870/871 devices have three memory
blocks. The Program Memory and Data Memory have
separate buses, so that concurrent access can occur,
and is detailed in this section. The EEPROM data
memory block is detailed in Section 3.0.
Additional information on device memory may be found
in the PICmicro
TM
Mid-Range MCU Family Reference
Manual (DS33023).
2.1 Program Memory Organization
The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have
2K x 14 words of FLASH program memory. Accessing
a location above the physically implemented address
will cause a wraparound.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1: PIC16F870/871 PROGRAM
MEMORY MAP AND STACK
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or
indirectly through the File Select Register FSR.
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
07FFh
0800h
RP<1:0> Bank
00 0
01 1
10 2
11 3
Note: EEPROM Data Memory description can
be found in Section 3.0 of this Data Sheet.