PIC16F870/871 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers • PIC16F870 • PIC16F871 Microcontroller Core Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two-cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • 2K x 14 words of FLASH Program Memory 128 x 8 bytes of Data Memory (RAM) 64 x 8 bytes of EEPROM Data Memory • Pinout compatible to the PIC16CXXX 28 and 40-pin devices •
PIC16F870/871 Pin Diagrams 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5 RC4 6 5 4 3 2 1 44 43 42 41 40 PLCC RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP/THV NC RB7/PGD RB6/PGC RB5 RB4 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MCLR/VPP/THV RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4 VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3 PIC16F870 DIP, SOIC, SSOP 18 19 20 21 22 23 24 25 26 27 282 PI
PIC16F870/871 Key Features PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) PIC16F870 PIC16F871 Operating Frequency DC - 20 MHz DC - 20 MHz RESETS (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) FLASH Program Memory (14-bit words) 2K 2K Data Memory (bytes) 128 128 EEPROM Data Memory 64 64 Interrupts 10 11 I/O Ports Ports A,B,C Ports A,B,C,D,E 3 3 Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Instruc
PIC16F870/871 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................. 11 3.0 Data EEPROM and Flash Program Memory..........................................................
PIC16F870/871 1.0 DEVICE OVERVIEW There are two devices (PIC16F870 and PIC16F871) covered by this data sheet. The PIC16F870 device comes in a 28-pin package and the PIC16F871 device comes in a 40-pin package. The 28-pin device does not have a Parallel Slave Port implemented. This document contains device specific information.
PIC16F870/871 FIGURE 1-2: PIC16F871 BLOCK DIAGRAM Device Program FLASH Data Memory Data EEPROM PIC16F871 2K 128 Bytes 64 Bytes 13 Program Memory 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4 RAM File Registers 8 Level Stack (13-bit) Program Bus 8 Data Bus Program Counter FLASH RAM Addr (1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO
PIC16F870/871 TABLE 1-1: PIC16F870 PINOUT DESCRIPTION DIP Pin# SOIC Pin# I/O/P Type OSC1/CLKI 9 9 I OSC2/CLKO 10 10 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, the OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP/THV 1 1 I/P ST Master Clear (Reset) input or programming voltage input or High Voltage Test mode control. This pin is an active low RESET to the device.
PIC16F870/871 TABLE 1-2: PIC16F871 PINOUT DESCRIPTION DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type OSC1/CLKI 13 14 30 I ST/CMOS(4) OSC2/CLKO 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP/THV 1 2 18 I/P ST Master Clear (Reset) input or programming voltage input or High Voltage Test mode control.
PIC16F870/871 TABLE 1-2: Pin Name PIC16F871 PINOUT DESCRIPTION (CONTINUED) DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
PIC16F870/871 NOTES: DS30569C-page 10 2000-2013 Microchip Technology Inc.
PIC16F870/871 2.0 MEMORY ORGANIZATION The PIC16F870/871 devices have three memory blocks. The Program Memory and Data Memory have separate buses, so that concurrent access can occur, and is detailed in this section. The EEPROM data memory block is detailed in Section 3.0. 2.2 The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.
PIC16F870/871 FIGURE 2-2: PIC16F870/871 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register File Address Indirect addr.
PIC16F870/871 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1: Address The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
PIC16F870/871 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(2) Bank 1 80h(4) INDF 81h OPTION_REG 82h(4) PCL 83h(4) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PS2 PS1 PS0 1111 1111 1111 1111 PD Z DC C 0001 1xxx 000q quuu Program Counter's (PC) Least Significant Byte IRP RP1 RP0
PIC16F870/871 TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(2) Bank 2 100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 102h(4) PCL Program Counter's (PC) Least Significant Byte 103h(4) STATUS 104h(4) FSR IRP RP1 RP0 0000 0000 0000
PIC16F870/871 2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F870/871 2.2.2.2 OPTION_REG Register The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT interrupt, TMR0 and the weak pull-ups on PORTB. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F870/871 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16F870/871 2.2.2.4 PIE1 Register The PIE1 register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16F870/871 2.2.2.5 PIR1 Register The PIR1 register contains the individual flag bits for the peripheral interrupts. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
PIC16F870/871 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt.
PIC16F870/871 2.2.2.7 PIR2 Register The PIR2 register contains the flag bit for the EEPROM write operation interrupt. . Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F870/871 2.2.2.8 PCON Register The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. Note: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16F870/871 2.3 PCL and PCLATH The Program Counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16F870/871 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing from opcode RP1: RP0 6 Bank Select Location Select 0 IRP 7 Bank Select 00 01 10 FSR Register 0 Location Select 11 00h 80h 100h 180h 7Fh FFh 17Fh 1FFh Data Memory(1) Bank 0 Note 1: Bank 1 Bank 2 Bank 3 For register file map detail see Figure 2-2. 2000-2013 Microchip Technology Inc.
PIC16F870/871 NOTES: DS30569C-page 26 2000-2013 Microchip Technology Inc.
PIC16F870/871 3.0 DATA EEPROM AND FLASH PROGRAM MEMORY The Data EEPROM and FLASH Program Memory are readable and writable during normal operation over the entire VDD range. A bulk erase operation may not be issued from user code (which includes removing code protection). The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are six SFRs used to read and write the program and data EEPROM memory.
PIC16F870/871 Write operations have two control bits, WR and WREN, and two status bits, WRERR and EEIF. The WREN bit is used to enable or disable the write operation. When WREN is clear, the write operation will be disabled. Therefore, the WREN bit must be set before executing a write operation. The WR bit is used to initiate the write operation. It also is automatically cleared at the end of the write operation. The interrupt flag EEIF is used to determine when the memory write completes.
PIC16F870/871 3.3 Reading the EEPROM Data Memory Reading EEPROM data memory only requires that the desired address to access be written to the EEADR register and clear the EEPGD bit. After the RD bit is set, data will be available in the EEDATA register on the very next instruction cycle. EEDATA will hold this value until another read operation is initiated or until it is written by firmware. The steps to reading the EEPROM data memory are: 1. 2. 3. 4. Write the address to EEDATA.
PIC16F870/871 3.5 Reading the FLASH Program Memory 3.6 Writing to the FLASH Program Memory Reading FLASH program memory is much like that of EEPROM data memory, only two NOP instructions must be inserted after the RD bit is set. These two instruction cycles that the NOP instructions execute, will be used by the microcontroller to read the data out of program memory and insert the value into the EEDATH:EEDATA registers. Data will be available following the second NOP instruction.
PIC16F870/871 At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) Since the microcontroller does not execute instructions during the write cycle, the firmware does not necessarily have to check either EEIF, or WR, to determine if the write had finished.
PIC16F870/871 3.10 FLASH Program Memory Write Protection The configuration word contains a bit that write protects the FLASH program memory, called WRT. This bit can only be accessed when programming the PIC16F870/871 devices via ICSP. Once write protection is enabled, only an erase of the entire device will disable it. When enabled, write protection prevents any writes to FLASH program memory. Write protection does not affect program memory reads.
PIC16F870/871 4.0 I/O PORTS FIGURE 4-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PIC® Mid-Range MCU Family Reference Manual (DS33023). 4.1 Data Bus D Q VDD WR Port Q CK P Data Latch PORTA and the TRISA Register PORTA is a 6-bit wide bi-directional port.
PIC16F870/871 TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/AN4 bit5 TTL Input/output or analog input.
PIC16F870/871 4.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F870/871 TABLE 4-3: Name PORTB FUNCTIONS Bit# Buffer (1) Function RB0/INT bit0 TTL/ST RB1 bit1 TTL RB2 bit2 TTL RB3/PGM bit3 TTL/ST(1) RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up.
PIC16F870/871 4.3 FIGURE 4-5: PORTC and the TRISC Register PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F870/871 4.4 FIGURE 4-6: PORTD and TRISD Registers PORTD BLOCK DIAGRAM (IN I/O PORT MODE) This section is not applicable to the PIC16F870. Data Bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. WR Port PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PIC16F870/871 4.5 PORTE and TRISE Register This section is not applicable to the PIC16F870. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs).
PIC16F870/871 REGISTER 4-1: TRISE REGISTER (ADDRESS: 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — Bit2 Bit1 Bit0 bit 7 bit 0 bit 7 Parallel Slave Port Status/Control Bits IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer
PIC16F870/871 TABLE 4-9: Name PORTE FUNCTIONS Bit# Buffer Type Function RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected.) RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected).
PIC16F870/871 4.6 Parallel Slave Port FIGURE 4-8: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is not implemented on the PIC16F870. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. It can directly interface to an 8-bit microprocessor data bus.
PIC16F870/871 FIGURE 4-9: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 4-10: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 4-11: Address REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name 08h PORTD 09h PORTE 89h TRISE 0Ch PIR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RE1 RE0 Port Data Latch when written: Port pins when re
PIC16F870/871 NOTES: DS30569C-page 44 2000-2013 Microchip Technology Inc.
PIC16F870/871 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2.
PIC16F870/871 5.2 Using Timer0 with an External Clock 5.3 When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns).
PIC16F870/871 TABLE 5-1: Address 01h,101h REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 Module’s Register GIE PEIE T0IE Value on: POR, BOR Value on all other RESETS xxxx xxxx uuuu uuuu INTE RBIE OPTION_REG RBPU INTEDG T0CS T0SE PSA T0IF INTF RBIF 0000 000x 0000 000u PS2 PS1 PS0 1111 1111 1111 1111 x = unknown, u = unchanged, - = unimplemented locations read as '0'.
PIC16F870/871 NOTES: DS30569C-page 48 2000-2013 Microchip Technology Inc.
PIC16F870/871 6.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>).
PIC16F870/871 6.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect, since the internal clock is always in sync. FIGURE 6-1: 6.2 Timer1 Counter Operation Timer1 may operate in either a Synchronous, or an Asynchronous mode, depending on the setting of the TMR1CS bit.
PIC16F870/871 6.4 Timer1 Operation in Asynchronous Counter Mode TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1).
PIC16F870/871 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L) 6.8 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 special event trigger. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.
PIC16F870/871 7.0 TIMER2 MODULE Register 7-1 shows the Timer2 control register. Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. Additional information on timer modules is available in the PIC® Mid-Range MCU Family Reference Manual (DS33023).
PIC16F870/871 7.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device RESET (POR, MCLR Reset, WDT Reset, or BOR) 7.2 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock. TMR2 is not cleared when T2CON is written.
PIC16F870/871 8.0 CAPTURE/COMPARE/PWM MODULES Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: Additional information on CCP modules is available in the PIC® Mid-Range MCU Family Reference Manual (DS33023) and in application note AN594, “Using the CCP Modules” (DS00594). TABLE 8-1: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Table 8-1 shows the resources and interactions of the CCP module.
PIC16F870/871 8.2 8.2.2 Capture Mode TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. • • • • 8.2.
PIC16F870/871 8.3 8.3.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>). Special Event Trigger RC2/CCP1 pin CCPR1H CCPR1L S R TRISC<2> Output Enable 8.3.
PIC16F870/871 8.4 8.4.1 PWM Mode (PWM) In Pulse Width Modulation mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F870/871 8.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
PIC16F870/871 TABLE 8-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on all other RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 0Bh,8Bh, INTCON 10Bh, 18Bh GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Address 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1
PIC16F870/871 9.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous - Master (half-duplex) • Synchronous - Slave (half-duplex) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.
PIC16F870/871 REGISTER 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Syn
PIC16F870/871 9.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate.
PIC16F870/871 TABLE 9-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz BAUD RATE (K) KBAUD % ERROR FOSC = 16 MHz SPBRG value (decimal) KBAUD % ERROR FOSC = 10 MHz SPBRG value (decimal) KBAUD % ERROR SPBRG value (decimal) 0.3 - - - - - - - - - 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.
PIC16F870/871 TABLE 9-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz FOSC = 16 MHz BAUD RATE (K) KBAUD % ERROR SPBRG value (decimal) 0.3 - - 1.2 - - 2.4 - FOSC = 10 MHz KBAUD % ERROR SPBRG value (decimal) - - - - - - - - - KBAUD % ERROR SPBRG value (decimal) - - - - - - - - - - 2.441 1.71 255 9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64 19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31 28.8 29.070 0.94 42 29.412 2.
PIC16F870/871 9.2 USART Asynchronous Mode enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty.
PIC16F870/871 When setting up an Asynchronous Transmission, follow these steps: 5. 1. 6. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 9.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 2. 3. 4. FIGURE 9-2: Enable the transmission by setting bit TXEN, which will also set bit TXIF.
PIC16F870/871 9.2.2 USART ASYNCHRONOUS RECEIVER is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software.
PIC16F870/871 When setting up an Asynchronous Reception, follow these steps: 1. 2. 3. 4. 5. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10.
PIC16F870/871 9.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT When setting up an Asynchronous Reception with Address Detect enabled: • Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • If interrupts are desired, then set enable bit RCIE. • Set bit RX9 to enable 9-bit reception. • Set ADDEN to enable address detect.
PIC16F870/871 FIGURE 9-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT START bit bit0 RC7/RX/DT (pin) bit1 bit8 STOP bit START bit bit0 bit8 STOP bit Load RSR Bit8 = 0, Data Byte Word 1 RCREG Bit8 = 1, Address Byte Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1.
PIC16F870/871 9.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16F870/871 TABLE 9-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x Name 0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch PIR1 18h RCSTA 19h TXREG USART Transmit Register 8Ch PIE1 PS
PIC16F870/871 9.3.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence.
PIC16F870/871 TABLE 9-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name 0Bh, 8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 0Ch PIR1 18h RCSTA 1Ah RCREG USART Receive Register 8Ch PIE1 PSPIE
PIC16F870/871 9.4 USART Synchronous Slave Mode When setting up a Synchronous Slave Transmission, follow these steps: Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 9.4.1 1. 2. 3. USART SYNCHRONOUS SLAVE TRANSMIT 4. 5.
PIC16F870/871 9.4.2 USART SYNCHRONOUS SLAVE RECEPTION When setting up a Synchronous Slave Reception, follow these steps: The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a “don't care” in Slave mode. 1. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP.
PIC16F870/871 NOTES: DS30569C-page 78 2000-2013 Microchip Technology Inc.
PIC16F870/871 10.0 ANALOG-TO-DIGITAL (A/D) CONVERTER MODULE The A/D module has four registers. These registers are: The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the other devices. The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation.
PIC16F870/871 REGISTER 10-2: ADCON1 REGISTER (ADDRESS: 9Fh) U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
PIC16F870/871 These steps should be followed for doing an A/D Conversion: 1. 2. 3. 4. Configure the A/D module: • Configure analog pins/voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit FIGURE 10-1: 5. 6. 7. Wait the required acquisition time.
PIC16F870/871 10.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 10-2.
PIC16F870/871 10.2 Selecting the A/D Conversion Clock For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selected.
PIC16F870/871 10.4 A/D Conversions acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample.
PIC16F870/871 10.5 A/D Operation During SLEEP Turning off the A/D places the A/D module in its lowest current consumption state. The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion.
PIC16F870/871 NOTES: DS30569C-page 86 2000-2013 Microchip Technology Inc.
PIC16F870/871 11.0 SPECIAL FEATURES OF THE CPU The PIC16F870/871 devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide Power Saving Operating modes and offer code protection.
PIC16F870/871 REGISTER 11-1: CP1 CP0 CONFIGURATION WORD (ADDRESS 2007h)(1) DEBUG — WRT CPD LVP BOREN CP1 CP0 PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit 0 (2) bit 13-12, bit 5-4 CP1:CP0: FLASH Program Memory Code Protection bits 11 = Code protection off 10 = Not supported 01 = Not supported 00 = Code protection on bit 11 DEBUG: In-Circuit Debugger Mode 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
PIC16F870/871 11.2 FIGURE 11-2: Oscillator Configurations 11.2.1 OSCILLATOR TYPES The PIC16F870/871 can be operated in four different Oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 11.2.
PIC16F870/871 TABLE 11-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Osc Type Crystal Freq. Cap. Range C1 Cap. Range C2 LP 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF XT HS 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes following this table. 11.2.
PIC16F870/871 11.3 RESET The PIC16F870/871 differentiates between various kinds of RESET: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET.
PIC16F870/871 11.4 Power-on Reset (POR) 11.7 A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details.
PIC16F870/871 TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP 1 Legend: x = don’t care, u = unchanged TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Re
PIC16F870/871 TABLE 11-6: Register PIR1 INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets WDT Reset PIC16F871 r000 -000 r000 -000 ruuu -uuu(1) PIC16F870 PIC16F871 0000 -000 0000 -000 uuuu -uuu(1) Devices PIC16F870 Wake-up via WDT or Interrupt PIC16F870 PIC16F871 ---0 ------0 ------u ----(1) PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu PIC16F870 PIC16F871 --00 0000 --uu uuuu --uu uuuu PIC16F8
PIC16F870/871 FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 11-6: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 11-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2000-2013 Microchip Technology Inc.
PIC16F870/871 FIGURE 11-8: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 11.10 Interrupts The PIC16F870/871 family has up to 14 sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, or the GIE bit.
PIC16F870/871 FIGURE 11-9: INTERRUPT LOGIC EEIF EEIE PSPIF PSPIE ADIF ADIE Wake-up (If in SLEEP mode) T0IF T0IE INTF INTE RCIF RCIE TXIF TXIE Interrupt to CPU RBIF RBIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF EEIF PIC18F870 Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes PIC18F871 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 11.10.
PIC16F870/871 11.11 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. For the PIC16F870/871 devices, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e.
PIC16F870/871 11.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin.
PIC16F870/871 11.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F870/871 FIGURE 11-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC PC+1 Inst(PC) = SLEEP Inst(PC - 1) PC+2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycl
PIC16F870/871 11.17 In-Circuit Serial Programming PIC16F870/871 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware to be programmed.
PIC16F870/871 12.0 INSTRUCTION SET SUMMARY Each PIC16F870/871 instruction is a 14-bit word, divided into an OPCODE, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. The PIC16F870/871 instruction set summary in Table 12-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 12-1 shows the opcode field descriptions.
PIC16F870/871 TABLE 12-2: PIC16F870/871 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f
PIC16F870/871 12.1 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW Syntax: [ label ] BCF Operands: 0 k 255 Operands: 0 f 127 0b7 Operation: (W) + k (W) Status Affected: C, DC, Z Operation: 0 (f) Description: The contents of the W register are added to the eight-bit literal 'k' and the result is placed in the W register. Status Affected: None Description: Bit 'b' in register 'f' is cleared.
PIC16F870/871 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16F870/871 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register.
PIC16F870/871 MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: No operation Operation: (f) (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected.
PIC16F870/871 RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
PIC16F870/871 SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. (f) destination) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in the W register.
PIC16F870/871 13.
PIC16F870/871 13.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 13.
PIC16F870/871 13.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F870/871 13.14 PICDEM 1 PIC MCU Demonstration Board 13.17 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC16F870/871 13.20 PICDEM 18R PIC18C601/801 Demonstration Board 13.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/De-multiplexed and 16-bit Memory modes.
PIC16F870/871 NOTES: DS30569C-page 116 2000-2013 Microchip Technology Inc.
PIC16F870/871 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.
PIC16F870/871 FIGURE 14-1: PIC16FXXX VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 20 MHz Frequency FIGURE 14-2: PIC16LFXXX VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V Eq 2.5V 2.0V Eq 4 MHz ti ua on n tio ua 2 1 10 MHz 20 MHz Frequency Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz; VDDAPPMIN = 2.0V - 3.0V Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN – 3.0V) + 10 MHz; VDDAPPMIN = 3.0V - 4.
PIC16F870/871 14.1 DC Characteristics: PIC16F870/871 (Industrial, Extended) PIC16LF870/871 (Commercial, Industrial) PIC16LF870/871 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial 0°C TA +70°C for Commercial PIC16F870/871 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param No.
PIC16F870/871 14.1 DC Characteristics: PIC16F870/871 (Industrial, Extended) PIC16LF870/871 (Commercial, Industrial) (Continued) PIC16LF870/871 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial 0°C TA +70°C for Commercial PIC16F870/871 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param No.
PIC16F870/871 14.2 DC Characteristics: PIC16F870/871 (Industrial) DC CHARACTERISTICS Param No. Sym VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2. Min Typ† Max Units Conditions with TTL buffer VSS — 0.15 VDD V For entire VDD range VSS — 0.8V V 4.5V VDD 5.5V with Schmitt Trigger buffer VSS — 0.
PIC16F870/871 14.2 DC Characteristics: PIC16F870/871 (Industrial) (Continued) DC CHARACTERISTICS Param No. Sym VOL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2. Min Typ† Max Units Conditions Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO (RC osc config) — — 0.
PIC16F870/871 14.3 DC Characteristics: PIC16F870/871 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Operating voltage VDD range as described in DC specification (Section ) DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Conditions with TTL buffer VSS — 0.15 VDD V For entire VDD range VSS — 0.8V V 4.5V VDD 5.5V with Schmitt Trigger buffer VSS — 0.
PIC16F870/871 14.3 DC Characteristics: PIC16F870/871 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Operating voltage VDD range as described in DC specification (Section ) DC CHARACTERISTICS Param No. Sym VOL Characteristic Min Typ† Max Units Conditions Output Low Voltage D080A I/O ports — — 0.6 V IOL = 7.0 mA, VDD = 4.5V D083A OSC2/CLKO (RC osc config) — — 0.6 V IOL = 1.2 mA, VDD = 4.
PIC16F870/871 14.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F870/871 FIGURE 14-3: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF Note: FIGURE 14-4: for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output PORTD and PORTE are not implemented on the PIC16F870. EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO DS30569C-page 126 2000-2013 Microchip Technology Inc.
PIC16F870/871 TABLE 14-1: Param No. Sym FOSC EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic External CLKI Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKI Period (Note 1) Oscillator Period (Note 1) Min Typ† Max Units Conditions DC — 4 MHz XT and RC Osc mode DC — 4 MHz HS Osc mode (-04) DC — 20 MHz HS Osc mode (-20) DC — 200 kHz DC — 4 MHz RC Osc mode 0.
PIC16F870/871 FIGURE 14-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 14-3 for load conditions. TABLE 14-2: Param No.
PIC16F870/871 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Osc Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 14-3 for load conditions. FIGURE 14-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 14-3: Param No.
PIC16F870/871 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 14-3 for load conditions. TABLE 14-4: Param No.
PIC16F870/871 FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 14-3 for load conditions. TABLE 14-5: Param No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Sym TccL TccH Characteristic * CCP1 input low time CCP1 input high time No Prescaler With Prescaler TccP CCP1 input period 53* TccR CCP1 output rise time 54* TccF CCP1 output fall time * † Standard(F) Extended(LF) Typ† Max Units 0.
PIC16F870/871 FIGURE 14-10: PARALLEL SLAVE PORT TIMING (PIC16F871 ONLY) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 14-3 for load conditions. TABLE 14-6: Param No.
PIC16F870/871 FIGURE 14-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 14-3 for load conditions. TABLE 14-7: Param No.
PIC16F870/871 TABLE 14-9: PIC16F870/871 (INDUSTRIAL) PIC16LF870/871 (INDUSTRIAL) Param Sym No. Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A06 EOFF Offset error — — <±1 LSb VREF = VDD = 5.
PIC16F870/871 FIGURE 14-13: A/D CONVERSION TIMING 1 TCY BSF ADCON0, GO (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 7 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 14-10: A/D CONVERSION REQUIREMENTS Param No. 130 Sym TAD Characteristic A/D clock period Min Typ† Max Units Standard(F) 1.
PIC16F870/871 NOTES: DS30569C-page 136 2000-2013 Microchip Technology Inc.
PIC16F870/871 15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F870/871 FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.4 5.5V 1.2 5.0V 1.0 I DD (mA) 4.5V 0.8 4.0V 3.5V 0.6 3.0V 0.4 2.5V 2.0V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.5 4.0 F OSC (MHz) FIGURE 15-4: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 2.0 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.
PIC16F870/871 FIGURE 15-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 90 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 80 5.5V 70 5.0V 60 IDD (uA) 4.5V 50 4.0V 3.5V 40 3.0V 30 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 F OS C (kH z ) FIGURE 15-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 120 110 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 100 5.0V 90 80 4.
PIC16F870/871 FIGURE 15-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25C) 4.0 3.3k 3.5 3.0 5.1k Freq (MHz) 2.5 2.0 10k 1.5 1.0 0.5 100k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 15-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25C) 2.0 1.8 1.6 3.3 k Freq (MHz) 1.4 1.2 5.1 k 1.0 0.8 0.6 10 k 0.4 0.2 100 k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V D D (V ) DS30569C-page 140 2000-2013 Microchip Technology Inc.
PIC16F870/871 FIGURE 15-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25C) 1.0 0.9 0.8 3.3 k Freq (MHz) 0.7 0.6 5.1 k 0.5 0.4 0.3 10 k 0.2 0.1 100 k 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 V D D (V) FIGURE 15-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100.00 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max (125C) 10.00 I PD ( A) Max (85C) 1.00 0.10 Typ (25C) 0.01 2.0 2.5 3.
PIC16F870/871 FIGURE 15-11: IBOR vs. VDD OVER TEMPERATURE 1.2 Note: 1.0 Device current in RESET depends on Oscillator mode, frequency and circuit. Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max RESET 0.6 I (mA) 0.8 Indeterminate State Typ RESET (25°C) 0.4 Device in SLEEP Device in RESET 0.2 Max SLEEP Typ SLEEP (25°C) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V D D (V) FIGURE 15-12: TYPICAL AND MAXIMUMITMR1 vs.
PIC16F870/871 FIGURE 15-13: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE 14 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 12 10 I WDT (uA) Max (85C) 8 Typ (25C) 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 15-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs.
PIC16F870/871 FIGURE 15-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO 125C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 40 125C 35 WDT Period (ms) 85C 30 25 25C 20 -40C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO 125C) 5.0 Max (-40C) 4.5 Typ (25C) VOH (V) 4.0 3.5 Min (125C) 3.
PIC16F870/871 FIGURE 15-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO 125C) 3.0 Max (-40C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.5 Typ (25C) VOH (V) 2.0 1.5 Min (125C) 1.0 0.5 0.0 0 5 10 15 20 25 I OH (-mA) FIGURE 15-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO 125C) 2.0 1.
PIC16F870/871 FIGURE 15-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO 125C) 3.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.5 VOL (V) 2.0 1.5 Max (125C) 1.0 Typ (25C) 0.5 Min (-40C) 0.0 0 5 10 15 20 25 I OL (-mA) FIGURE 15-20: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO 125C) 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.
PIC16F870/871 FIGURE 15-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO 125C) 4.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 4.0 3.5 Max High (125C) 3.0 Min High (-40C) VIN (V) 2.5 2.0 Max Low (125C) 1.5 Min Low (-40C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 15-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO 125C) 3.
PIC16F870/871 NOTES: DS30569C-page 148 2000-2013 Microchip Technology Inc.
PIC16F870/871 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC 0317017 Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP PIC16F870-I/SO 0310017 Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC16F870/871 Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30569C-page 150 PIC16F871-I/P 0312017 Example PIC16F871 -I/PT 0320017 Example PIC16F871 -I/L 0320017 2000-2013 Microchip Technology Inc.
PIC16F870/871 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.
PIC16F870/871 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16F870/871 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16F870/871 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 1 n E A2 A L c B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.
PIC16F870/871 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16F870/871 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3 A2 35 A B1 B c E2 Units Dimension Limits n p A1 p D2 INCHES* MIN NOM 44 .050 11 .165 .173 .145 .153 .028 .020 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .
PIC16F870/871 APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (December 1999) DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Original data sheet for the PIC16F870/871 family. Revision B (April 2003) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section 14.0 have been updated and there have been minor corrections to the data sheet text.
PIC16F870/871 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC17C756 to a PIC18F8720. Not Applicable APPENDIX D: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e.
PIC16F870/871 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration.” This Application Note is available as Literature Number DS00726. 2000-2013 Microchip Technology Inc.
PIC16F870/871 NOTES: DS30569C-page 160 2000-2013 Microchip Technology Inc.
PIC16F870/871 INDEX A A/D ...................................................................................... 79 Acquisition Requirements ........................................... 82 ADCON0 Register....................................................... 79 ADCON1 Register....................................................... 79 ADIF Bit....................................................................... 80 ADRESH Register....................................................... 79 ADRESL Register ...
PIC16F870/871 D Data EEPROM .................................................................... 27 Associated Registers .................................................. 32 Code Protection .......................................................... 31 Reading....................................................................... 29 Spurious Write Protection ........................................... 31 Write Verify ................................................................. 31 Writing to ...........
PIC16F870/871 Interrupts, Enable Bits Global Interrupt Enable (GIE Bit) .......................... 18, 96 Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) ...................................................... 18, 97 Peripheral Interrupt Enable (PEIE Bit) ........................ 18 RB0/INT Enable (INTE Bit) ......................................... 18 TMR0 Overflow Enable (T0IE Bit)............................... 18 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ........................
PIC16F870/871 PORTC.............................................................................. 7, 8 Associated Registers .................................................. 37 PORTC Register ......................................................... 37 RC0/T1OSO/T1CKI Pin ............................................ 7, 8 RC1/T1OSI Pin ......................................................... 7, 8 RC2/CCP1 Pin .......................................................... 7, 8 RC3 Pin...........................
PIC16F870/871 STATUS Register ......................................................... 13, 15 PD Bit.......................................................................... 91 TO Bit.......................................................................... 91 Synchronous Master Reception Associated Registers .................................................. 75 Synchronous Master Transmission Associated Registers ..................................................
PIC16F870/871 U W Universal Synchronous Asynchronous Receiver Transmitter. See USART USART ................................................................................ 61 Address Detect Enable (ADDEN Bit) .......................... 62 Asynchronous Mode ................................................... 66 Asynchronous Receive ............................................... 68 Asynchronous Receive (9-bit Mode) ........................... 70 Asynchronous Receive with Address Detect.
PIC16F870/871 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F870/871 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F870/871 PIC16F870/871 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC16F870, PIC16F870T; VDD range 4.0V to 5.5V PIC16F871, PIC16F871T ; VDD range 4.0V to 5.5V PIC16LF870X, PIC16LF870T; VDD range 2.0V to 5.5V PIC16LF871X, PIC16LF871T; VDD range 2.0V to 5.
PIC16F870/871 NOTES: 2000-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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