Datasheet

PIC16F87/88
DS30487D-page 92  2002-2013 Microchip Technology Inc.
10.3 SSP I
2
C Mode Operation
The SSP module in I
2
C mode fully implements all slave
functions, except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RB4/
SCK/SCL pin, which is the clock (SCL) and the RB1/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISB<4,1> bits.
To ensure proper communication of the I
2
C Slave mode,
the TRIS bits (TRISx [SDA, SCL]) corresponding to the
I
2
C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>)
of the port containing the I
2
C pins (PORTx [SDA, SCL])
are changed in software during I
2
C communication
using a Read-Modify-Write instruction (BSF, BCF), then
the I
2
C mode may stop functioning properly and I
2
C
communication may suspend. Do not change any of the
TRISx bits (TRIS bits of the port containing the I
2
C pins)
using the instruction BSF or BCF during I
2
C communica-
tion. If it is absolutely necessary to change the TRISx
bits during communication, the following method can be
used:
EXAMPLE 10-1:
The SSP module functions are enabled by setting SSP
Enable bit, SSPEN (SSPCON<5>).
FIGURE 10-5: SSP BLOCK DIAGRAM
(I
2
C™ MODE)
The SSP module has five registers for I
2
C operation:
• SSP Control register (SSPCON)
• SSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer register (SSPBUF)
• SSP Shift register (SSPSR) – Not directly
accessible
• SSP Address register (SSPADD)
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Controlled Master mode
•I
2
C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Controlled Master mode
•I
2
C Firmware Controlled Master mode operation
with Start and Stop bit interrupts enabled; slave is
Idle
Selection of any I
2
C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISB bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I
2
C module.
Additional information on SSP I
2
C operation may be
found in the “PIC
®
Mid-Range MCU Family Reference
Manual” (DS33023).
MOVF TRISC, W ; Example for an 18-pin part such as the PIC16F818/819
IORLW 0x18 ; Ensures <4:3> bits are ‘11’
ANDLW B’11111001’ ; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
MOVWF TRISC
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop Bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P Bits
(SSPSTAT Reg)
RB4/SCK/
RB1/
Shift
Clock
MSb
SDI/
LSb
SDA
SCL