Datasheet

PIC16F87/88
DS30487D-page 62  2002-2013 Microchip Technology Inc.
FIGURE 5-11: BLOCK DIAGRAM OF RB3/PGM/CCP1
(3)
PIN
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
Q
D
EN
Data Bus
WR
WR
RD TRISB
RD PORTB
Weak
Pull-up
RD PORTB
I/O pin
(1)
TTL
Input
Buffer
TRIS Latch
PORTB
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU
bit.
3: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.
0
1
CCP
To PGM or CCP
CCP1M<3:0> = 1000, 1001, 11xx and CCPMX = 0
CCP1M<3:0> = 0100, 0101, 0110, 0111 and CCPMX = 0
or LVP = 1
TRISB