Datasheet

 2002-2013 Microchip Technology Inc. DS30487D-page 43
PIC16F87/88
4.7 Power-Managed Modes
4.7.1 RC_RUN MODE
When SCS bits are configured to run from the INTRC,
a clock transition is generated if the system clock is
not already using the INTRC. The event will clear the
OSTS bit, switch the system clock from the primary
system clock (if SCS<1:0> = 00) determined by the
value contained in the configuration bits, or from the
T1OSC (if SCS<1:0> = 01) to the INTRC clock option
and shut down the primary system clock to conserve
power. Clock switching will not occur if the primary
system clock is already configured as INTRC.
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed and the
IRCF bits in the OSCCON register are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after 4 ms (approx.).
After a clock switch has been executed, the OSTS bit
is cleared, indicating a low-power mode and the
device does not run from the primary system clock.
The internal Q clocks are held in the Q1 state until
eight falling edge clocks are counted on the INTRC
oscillator. After the eight clock periods have transpired,
the clock input to the Q clocks is released and opera-
tion resumes (see Figure 4-7).
FIGURE 4-7: TIMING DIAGRAM FOR XT, HS, LP, EC AND EXTRC TO RC_RUN MODE
Q4Q3Q2
OSC1
SCS<1:0>
Program
PC + 1PC
Note 1: T
INP =32s typical.
2: T
OSC = 50 ns minimum.
3: T
SCS =8 TINP.
4: T
DLY =1 TINP.
Q1
INTOSC
Q1
TSCS
(3)
Counter
Q1
TDLY
(4)
TINP
(1)
System
Clock
TOSC
(2)
Q3Q2 Q4 Q1 Q2
PC + 3
Q3 Q4
Q1
PC + 2