Datasheet

PIC16F87/88
DS30487D-page 42  2002-2013 Microchip Technology Inc.
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0>
000)
1. IRCF bits are modified to a different INTOSC/
INTOSC postscaler frequency.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. The IOFS bit is set.
5. Oscillator switchover is complete.
4.6.6 OSCILLATOR DELAY UPON
POWER-UP, WAKE-UP AND
CLOCK SWITCHING
Table 4-3 shows the different delays invoked for
various clock switching sequences. It also shows the
delays invoked for POR and wake-up.
TABLE 4-3: OSCILLATOR DELAY EXAMPLES
Clock Switch
Frequency Oscillator Delay Comments
From To
Sleep/POR
INTRC
T1OSC
31.25 kHz
32.768 kHz
CPU Start-up
(1)
Following a wake-up from Sleep mode or
POR, CPU start-up is invoked to allow the
CPU to become ready for code execution.
INTOSC/
INTOSC
Postscaler
125 kHz-8 MHz
4 ms (approx.) and
CPU Start-up
(1)
INTRC/Sleep EC, RC DC – 20 MHz
INTRC
(31.25 kHz)
EC, RC DC – 20 MHz
Sleep LP, XT, HS 32.768 kHz-20 MHz
1024 Clock Cycles
(OST)
Following a change from INTRC, an OST
of 1024 cycles must occur.
INTRC
(31.25 kHz)
INTOSC/
INTOSC
Postscaler
125 kHz-8 MHz 4 ms (approx.)
Refer to Section 4.6.4 “Modifying the
IRCF Bits” for further details.
Note 1: The 5-10 s start-up delay is based on a 1 MHz system clock.