Datasheet

PIC16F87/88
DS30487D-page 20  2002-2013 Microchip Technology Inc.
2.2.2.4 PIE1 Register
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE
(1)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
(1)
1 = Enabled
0 = Disabled
Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
bit 5 RCIE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TXIE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown