Datasheet

PIC16F87/88
DS30487D-page 152  2002-2013 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0  f  127
0  b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ‘b’ in register ‘f’ = 0, the next
instruction is executed.
If bit ‘b’ = 1, then the next
instruction is discarded and a NOP
is executed instead, making this a
2T
CY instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0  f  127
0  b  7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ‘b’ in register ‘f’ = 1, the next
instruction is executed.
If bit ‘b’, in register ‘f’, = 0, the next
instruction is discarded and a NOP
is executed instead, making this a
2 T
CY instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0  k  2047
Operation: (PC) + 1  TOS,
k  PC<10:0>,
(PCLATH<4:3>)  PC<12:11>
Status Affected: None
Description: Call subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0  f  127
Operation: 00h  (f),
1  Z
Status Affected: Z
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W),
1  Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h  WDT,
0  WDT prescaler,
1  TO
,
1  PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO
and PD are set.