Datasheet

 2002-2013 Microchip Technology Inc. DS30487D-page 15
PIC16F87/88
Bank 1
80h
(2)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
26, 135
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
18, 69
82h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000
135
83h
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx
17
84h
(2)
FSR Indirect Data Memory Address Pointer xxxx xxxx
135
85h TRISA TRISA7 TRISA6 TRISA5
(3)
PORTA Data Direction Register (TRISA<4:0>) 1111 1111
52, 126
86h TRISB PORTB Data Direction Register 1111 1111 58, 85
87h
— Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah
(1,2)
PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000
135
8Bh
(2)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
19, 69,
77
8Ch PIE1
—
ADIE
(4)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000
20, 80
8Dh PIE2 OSFIE CMIE —EEIE — — — — 00-0 ---- 22, 34
8Eh PCON — — — — — —PORBOR ---- --0q
24
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 -000 0000 40
90h OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 38
91h
— Unimplemented —
—
92h PR2 Timer2 Period Register 1111 1111 80, 85
93h SSPADD Synchronous Serial Port (I
2
C™ mode) Address Register 0000 0000
95
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000
88, 95
95h — Unimplemented
— —
96h — Unimplemented
— —
97h — Unimplemented
— —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 97, 99
99h SPBRG Baud Rate Generator Register 0000 0000 99, 103
9Ah — Unimplemented
— —
9Bh ANSEL
(4)
— ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 -111 1111
120
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 121,
126, 128
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 126, 128
9Eh ADRESL
(4)
A/D Result Register Low Byte xxxx xxxx
120
9Fh ADCON1
(4)
ADFM ADCS2 VCFG1 VCFG0 — — — — 0000 ----
52, 115,
120
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Details
on
page
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
4: PIC16F88 device only.