Datasheet

PIC16F87/88
DS30487D-page 142  2002-2013 Microchip Technology Inc.
REGISTER 15-3: WDTCON: WATCHDOG CONTROL REGISTER (ADDRESS 105h)
TABLE 15-6: SUMMARY OF WATCHDOG TIMER REGISTERS
U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
(1)
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Prescale
Value Rate
0000 =1:32
0001 =1:64
0010 =1:128
0011 =1:256
0100 =1:512
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16394
1010 = 1:32768
1011 = 1:65536
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
(1)
1 = WDT is turned on
0 = WDT is turned off
Note 1: If WDTEN configuration bit = 1, then WDT is always enabled, irrespective of this
control bit. If WDTEN configuration bit = 0, then it is possible to turn WDT on/off with
this control bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
2007h Configuration bits
LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0
105h WDTCON
— — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 15-1 for operation of these bits.