Datasheet

PIC16F87/88
DS30487D-page 14  2002-2013 Microchip Technology Inc.
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Details
on
page
Bank 0
00h
(2)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 26, 135
01h TMR0 Timer0 Module Register xxxx xxxx 69
02h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000
03h
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 17
04h
(2)
FSR Indirect Data Memory Address Pointer xxxx xxxx 135
05h PORTA PORTA Data Latch when written; PORTA pins when read (PIC16F87)
PORTA Data Latch when written; PORTA pins when read (PIC16F88)
xxxx 0000
xxx0 0000
52
06h PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87)
PORTB Data Latch when written; PORTB pins when read (PIC16F88)
xxxx xxxx
00xx xxxx
58
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah
(1,2)
PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000 135
0Bh
(2)
INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 19, 69,
77
0Ch PIR1 —ADIF
(4)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 21, 77
0Dh PIR2 OSFIF CMIF — EEIF — — — — 00-0 ---- 23, 34
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 77, 83
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 77, 83
10h T1CON — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 72, 83
11h TMR2 Timer2 Module Register 0000 0000 80, 85
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 80, 85
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 90, 95
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 89, 95
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 83, 85
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 83, 85
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 81, 83
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 98, 99
19h TXREG AUSART Transmit Data Register 0000 0000 103
1Ah RCREG AUSART Receive Data Register 0000 0000 105
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH
(4)
A/D Result Register High Byte xxxx xxxx 120
1Fh ADCON0
(4)
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 114, 120
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
4: PIC16F88 device only.